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ADS1260: SCLK timing between 8 bit and 9 bit and so on

Noriyuki Takahashi
Genius 9245 points
Part Number: ADS1260

Hi team

Looking at figure 76&77 on the datasheet,  it seems that the time of SCLKs between 8bit and 9bit, 16bit and 17bit and so on is longer than others.

How should we understand the longer time? Are there any requirements for the SCLK?

Regards,

Noriyuki Takahashi

  • 0
    TI__Mastermind 35520 points

    Hi Noriyuki,

    This figure shows the timing format defined for RDATA COMAND in table 21. The RDATA COMMAND requires variable lengths in multiples of  byte (8-bit). When the polarity of your SPI interface is configured as "0" and your microcontroller is sending data to ADC in 8-bit byte format., the SCLK will be automatically low voltage during idle status. 

    Thanks&Regards,

    Dale

  • 0 in reply to Dale Li
    TI__Genius 9245 points

    Hi Dale,

    When the polarity of your SPI interface is configured as "0", can ADS1260 accept that the period of idle status be same with the Low period of SCLK?

    I want to understand there are any restrictions of the period of idle status for ADS1260.

    Regards,

    Noriyuki Takahashi

  • 0 in reply to Noriyuki Takahashi
    TI__Mastermind 35520 points

    Hi Noriyuki,

    When the polarity of SPI is "0", the idle status of SCLK should be low, so there is no problem for the ADC. Also, notice that the operations in the timing above are performed in the form of bytes.

    Regards,

    Dale

  • 0 in reply to Dale Li
    TI__Genius 9245 points

    Dale,

    I think my question is not conveyed to you...

    My questions is.. are there any requirements for the time during the idle status of SCLK is low?

    I want to confirm whether the time during the idle status is same with tw(SCL) or longer than tw(SCL). This is because In the figure 76, the time of SCLKs between 8bit and 9bit is longer than others and it seems that the time during the idle status needs to be longer than the certain time.

    Does this make sense?

    Regards,

    Noriyuki Takahashi

  • 0 in reply to Noriyuki Takahashi
    TI__Mastermind 35520 points

    Noriyuki,

     As I said in previous post, there is no problem for the ADC since the operations in the timing above are performed in the form of bytes. This means a delay can be inserted  between SPI bytes as needed, the ADC can accept either continuous pulses or 8-pulse stream with a delay (idle status) on SCLK from your microcontroller, this delay or idle status does not have a limit to pulse duration time (twSCL).

    Regards,

    Dale