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ADS1298 Programming and data acquire with FPGA

Giuseppe Landolfi
Prodigy 100 points

Other Parts Discussed in Thread: ADS1298

 

Hi, 

 I'm trying to program ads1298 and acquire data with FPGA . 

In attachment I share the VHDL code and the simulation pictures. I like to know if it is correct what I did. Must I change anything?

Thank you very much.

 

0474.ADS1298 VHDL.zip

CLKSEL and PWDN tied permanently low.

Wait for 1s for Power-On Reset (t_rst = 1.48us), Issue reset pulse, wait for 18t_clk (9.77us), CS tied permanently low:

Set START = 1 before send RDATAC command, sclk = 480kHz,  t_sdecode = 4,166us:

RDATAC:

  • 0
    Prodigy 100 points

    I followed the datasheet's figure 64: Initial Flow at Power-Up.

  • 0 in reply to Giuseppe Landolfi
    TI__Guru**** 182551 points

    Hi Guiseppe,

    I gave your test bench plots on the ADS1298 a quick look over and don't see anything that jumps out as being 'wrong' with the setup.  I would like to suggest that you keep a hook in your code, at least initially for debug purposes, that allows you to toggle the /CS input.  If for some reason you have noise/glitches on the SCLK, you can run into a situation where your SPI communications seem to not respond, or respond with unexpected results.  Toggling the /CS line will reset the SPI interface without totally resetting the device registers.