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DAC3482EVM: CDCE62005 Register in Config File does not map to valid settings

Part Number: DAC3482EVM
Other Parts Discussed in Thread: DAC3482, , CDCE62005

For the DAC3482EVM, there is one register configuration file provided as a  reference:  "DAC3482_FDAC_1228p8MHz_4xint_NCO_30MHz_QMCon.txt"
This configures the DAC3482 and the CDCE62005 registers.  The register  CDCE62005 x3 entry in this file is defined as "C10C0003".  When I review the CDCE62005 manual for this register, the specified bit settings are not consistent with the manual.  Here is the relevant manual page from the CDCE62005 manual:

The value 0xC10C0003 translates to (for these subset of bits)
Bit 21 = 0
Bit 22 = 0
Bit 23 = 0 
Bit 24 = 0
Bit 25 = 0
Bit 26 = 1
Bit 27 = 1

It is not clear from the CDCE62005 manual what the config file attempting to achieve.  This bit mapping does not appear to be a valid combination.  I believe this is important, because this clock Drives the FPGA clock pins, so I'm guessing its important.  

  • Hi Andrew,

    there are total of 8 nibble (4x bits) in each register.

    The first 7 nibbles are to set the first 28 bits in the RAM bits ranging from 27 all the way down to 0. The last nibble is the register address

    In your example of register 3 above,

    Bit[27 to 22] of 7b110000 forms LVDS output in outbuffsely3. We should technically set P-output and N-output to also to be "inverting" to form the first nibble to be 0xE to conform to the advise LVDS level. We have been measuring LVDS output from the CDCE62005 without the P-output and N-output to be inverting and so far the EVMs are functional. 

    -Kang

  • OK, thanks for the explanation.  It was not clear from the datasheet that this was valid combination, but I understand that in LVDS mode the lower control bits are redundant and presumably ignored by the hardware in LVDS mode.  

    Sorry, just grasping as straws trying to figure out how to get the eval hardware to generate something that makes any sense. 

  • Thanks. We have actually measured the output swing to confirm this is indeed LVDS output.