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ADC3421: Maximum capacitance on VCM

Part Number: ADC3421
Other Parts Discussed in Thread: OPA4991

Hi,

What is the maximum capacitance I can put on the VCM pin.  I am using VCM to bias my ac coupled inputs and I am getting some crosstalk and noise coupling between channels - I believe via VCM.  Currently I see about 15mV of noise on VCM.  I would expect a significant amount of the noise should be eliminated as it will be common mode but it seems like there is still some effect on the signal.

Thanks

  • Yes, Vcm can be a typical conduit for crosstalk and interference.  Typically we use 0.1 uF for bypassing.  If needed/desired, this can be increased up to 1 uF.  There is no specified maximum capacitance on that pin.

    --RJH

  • Is it possible to send you my schematic for review?  I have attached it to this post.  I am considering using OPA4991 to buffer VCM from the adc separately for each adc input.  I am just not sure if that is necessary since any crosstalk between the channels should appear as common mode.

  • Hi Daniel,

    I have reviewed your schematic, and have a few comments.

    It appears that one wire data output is being used. Please ensure that the sampling clock rate is not below 15 MSPS as per Table 3 on page 44 of datasheet.

    As you mentioned about adding a buffer for VCM, I'm not entirely convinced that this is required, but would be the safest route to take. The VCM has 10 mA of drive capacity, so I don't think that should be an issue either.

    Best Regards,

    Dan

  • Is there any way of simulating this the effect of common mode noise in TINA?  We are sampling at 25MSPs using a 100MHz reference clock and dividing it down by 4 in the adc.  I am not sure how register 0x13 should be set.  It looks like we could set LOW SPEED ENABLE to 00 or 10.  It is not clear what that does.  Finally does using the chopper or dither functions increase phase noise/sampling jitter at all?

    Thanks,

    Dan

  • Hi Dan,

    I am not certain how VCM noise could be simulated in terms of the effect that it may have on the sampled ADC output data. As you mentioned before, if the VCM noise is common on both differential inputs (P/N), the noise should be effectively subtracted out during the sampling process.

    For register 0x13, please write 0x02 (1 wire, 25 MSPS). This register helps to ensure that the on-chip PLL that produces the data serialization clock remains locked when at lower sampling rates. Since you are right at the boundary of 25 MSPS, I would go ahead and set this register as described.

    Dither and Chopper do not impact the phase noise performance.

    Best Regards,

    Dan

  • I was also wondering if my drive circuit for the analog inputs needs any extra series resistance or extra filters to minimize the impact of the kick-back noise from the adc? (see page 67 of datasheet).  My drive circuit is attached.

    thanks,6013.TI adc review.pdf

    Dan

  • Hi Dan,

    It looks like you have about a 1.5 MHz LPF anit-aliasing filter on the output of your FDA (U21), so this should provide some attenuation for the kick-back noise. It may be prudent to place 0 ohm series resistors at the analog input pins of the U8 ADC (pins 8,9,12,13,30,31,34,35) in case some series resistance is needed.

    Additionally, looking at pg 67, Figure 183, including the 39 nH/50 ohm LPF and 50ohm/22pf/50ohm LPF filters will provide the most attenuation for the kickback noise. These values will need to be adjusted to ensure that your anti-aliasing requirements are met. However, since the sampling rate is fairly low (25 MSPS) compared to the other parts in this family (Up to 125 MSPS), I believe that the kickback noise will not be a critical issue since most of the noise will be attenuated within the acquisition phase (Ts/2) of the sampling process.

    In this case, I think that you can add the foot prints (if size constraints allow) for both of the aforementioned filters, but only use them if needed.

    Hope that helps.

    Best Regards,

    Dan