DAC80508: Maximum SCLK Speed During Read

Don,

Generally the maximum SCLK speed is not determined by the drive strength of the digital lines.

The SCLK speed is determined primarily by the internal setup and routing of the digital sections of the device. When digital sections are designed, there are checks run to see that the the setup and hold times are not violated through all the blocks. With digital sections that run up through many thousands of gates, the timing must be checked for all those violations, through different model characteristics. These characteristics include sets of models for faster and slower devices through process and over temperature. Verification of the internal digital timing will determine the maximum clock speed.

Joseph Wu

Thanks Joseph,

Appreciate the speedy response.    What's your opinion on the second part of my question?

For example, assuming FSDO = 0, VIO = 3.3V, and given the figure below; would we be able to use SCLK = 50MHz for frame #1, and then SCLK = 18MHz for frame #2?  

Don

Don,

I think I understand your question now. You want to know if the actual read command be sent in at the 50MHz clock and then have the read be clocked out at the 18HMz clock.

I'm sorry but I don't definitively know the answer to that one. The problem is that I'm not sure what prompted the limits to the digital clock rate for either the write or the read for the device. I would suspect that you could clock in the read command at the 50MHz because the device should be able to parse the read command as it would for any command. However, going by the description, I would say the read command is part of the read and to be safe I would use the 18MHz clock.

If this is important, I can check with design and see if they have an answer. However, I'm not entirely sure they'd be able to answer this one without running some simulations. Just let me know.

Joseph Wu

Thanks Joseph,

Please do run it by design.   Looking forward to an answer on this one.

Don