DAC38J82: Rising temperature appears DAC errors

Part Number: DAC38J82
Other Parts Discussed in Thread: LMK04828, TSW38J84EVM

Good day to all!

We use the DAC38J82 and it works fine, but when the DAC temperature is more than 45 degrees, errors appear on the JESD204B lines. The number of errors can be different from 2-3 per hour to errors that go constantly. The following errors appear: code synchronization error, 8b/10b not-in-table code error, 8b/10b disparity error, read_error, read_empty.

Our scheme:

When there are JESD errors, sometimes SYNC goes to zero:

During normal operation, the SYNC is one:

When the temperature decreases, errors disappear. What could be the problem?

  • LMK04828 configuration is in file.

    5545.LMK04828.txt
    0x000 0x10
    0x002 0x00
    0x100 0x12
    0x101 0x55
    0x103 0x01
    0x104 0x20
    0x105 0x00
    0x106 0xF0
    0x107 0x61
    0x108 0x12
    0x109 0x55
    0x10B 0x00
    0x10C 0x00
    0x10D 0x00
    0x10E 0xF9
    0x10F 0x00
    0x110 0x08
    0x111 0x55
    0x113 0x00
    0x114 0x00
    0x115 0x00
    0x116 0xF9
    0x117 0x00
    0x118 0x18
    0x119 0x55
    0x11B 0x00
    0x11C 0x20
    0x11D 0x00
    0x11E 0xF9
    0x11F 0x00
    0x120 0x72
    0x121 0x55
    0x123 0x01
    0x124 0x20
    0x125 0x00
    0x126 0xF0
    0x127 0x66
    0x128 0x08
    0x129 0x55
    0x12B 0x00
    0x12C 0x00
    0x12D 0x00
    0x12E 0xF9
    0x12F 0x00
    0x130 0x12
    0x131 0x55
    0x133 0x01
    0x134 0x20
    0x135 0x00
    0x136 0xF1
    0x137 0x01
    0x138 0x06
    0x139 0x02
    0x13A 0x00
    0x13B 0x2D
    0x13C 0x00
    0x13D 0x08
    0x13E 0x03
    0x13F 0x00
    0x140 0x00
    0x141 0x00
    0x142 0x00
    0x143 0x12
    0x144 0xFF
    0x145 0x7F
    0x146 0x10
    0x147 0x1A
    0x148 0x02
    0x149 0x42
    0x14A 0x33
    0x14B 0x16
    0x14C 0x00
    0x14D 0x00
    0x14E 0xC0
    0x14F 0x7F
    0x150 0x03
    0x151 0x02
    0x152 0x00
    0x153 0x00
    0x154 0x78
    0x155 0x00
    0x156 0x7D
    0x157 0x00
    0x158 0x96
    0x159 0x06
    0x15A 0x00
    0x15B 0xD4
    0x15C 0x20
    0x15D 0x00
    0x15E 0x00
    0x15F 0x0B
    0x160 0x00
    0x161 0x05
    0x162 0x44
    0x163 0x00
    0x164 0x00
    0x165 0x0A
    0x166 0x00
    0x167 0x00
    0x168 0x3F
    0x169 0x59
    0x16A 0x20
    0x16B 0x00
    0x16C 0x00
    0x16D 0x00
    0x16E 0x13
    0x17C 0x15
    0x17D 0x0F
    

  • DAC38J82 configuration is in file.

    DAC38J82.txt
    0x00 0xA118
    0x01 0x0003
    0x02 0x2082
    0x03 0xF000
    0x04 0xFFFF
    0x05 0xFF07
    0x06 0xFFFF
    0x07 0x3501
    0x08 0x0342
    0x09 0x1FB7
    0x0A 0x0000
    0x0B 0x0000
    0x0C 0x01CD
    0x0D 0x01E0
    0x0E 0x0400
    0x0F 0x0400
    0x10 0x00E9
    0x11 0x0000
    0x12 0x0000
    0x13 0x0000
    0x14 0x0000
    0x15 0x0000
    0x16 0x0000
    0x17 0x0000
    0x18 0x0000
    0x19 0x0000
    0x1A 0x0000
    0x1B 0x3408
    0x1E 0x9999
    0x1F 0x9980
    0x20 0x8008
    0x22 0x1B11
    0x23 0x01FF
    0x24 0x0030
    0x25 0x2000
    0x26 0x0000
    0x2D 0x0001
    0x2E 0xFFFF
    0x2F 0x0004
    0x30 0x0000
    0x31 0x4403
    0x32 0x0720
    0x33 0xED30
    0x34 0x0000
    0x3B 0x9800
    0x3C 0x8050
    0x3D 0x0088
    0x3E 0x0108
    0x3F 0x0000
    0x41 0x0000
    0x42 0x0000
    0x43 0x0000
    0x44 0x0000
    0x46 0x0044
    0x47 0x19C8
    0x48 0x3143
    0x49 0x0000
    0x4A 0x0321
    0x4B 0x0801
    0x4C 0x0901
    0x4D 0x0100
    0x4E 0x0F0F
    0x4F 0x1C41
    0x50 0x0000
    0x51 0x00DF
    0x52 0x00FF
    0x53 0x0000
    0x54 0x00FF
    0x55 0x00FF
    0x56 0x0000
    0x57 0x00FF
    0x58 0x00FF
    0x59 0x0000
    0x5A 0x00FF
    0x5B 0x00FF
    0x5C 0x1133
    0x5E 0x0000
    0x5F 0x0123
    0x60 0x5764
    0x61 0x0211
    0x64 0x0703
    0x65 0x0703
    0x66 0xFF0F
    0x67 0xBF0E
    0x68 0xDF0F
    0x69 0xEF0F
    0x6A 0xFF0F
    0x6B 0xE704
    0x6C 0x0006
    0x6D 0x00F0
    0x6E 0x0000
    0x6F 0x0000
    0x70 0x0000
    0x71 0x0000
    0x72 0x0000
    0x73 0x0000
    0x74 0x0000
    0x75 0x0070
    0x76 0x0000
    0x77 0x0000
    0x78 0x0000
    0x79 0x0000
    0x7A 0x0000
    0x7B 0x0000
    0x7C 0x0000
    0x7D 0x0000
    0x7F 0x800A

  • Evgeniy,

    When SYNC goes low at higher temps, is it staying low? Is the FPGA sending the K28.5 characters during this time? Have you tried using cold spray to isolate the issue? If you have a can of cold spray, apply it on the DAC or LMK or the FPGA, one part at a time to see if it helps the issue. Try using a larger value for K and RBD. Just make sure RBD never exceeds the K value. Does slowing the serdes help any? The DAC has an option to do eyescan on the individual lanes. Have you tried using this feature?

    Regards,

    Jim

     

  • Jim,

    > When SYNC goes low at higher temps, is it staying low?
    No, when SYNC gets low it gets high after a while, then it can go low again and so on.  

    > Is the FPGA sending the K28.5 characters during this time?
    Yes, when SYNC goes low then FPGA starts transmitting K28.5.

    > Have you tried using cold spray to isolate the issue?
    We did it on evaluation boards MPF300-EVAL-KIT and TSW38J84EVM. We heated up separately the DAC and FPGA, but there were no errors.
    We need a little more time to do this on our board, we plan to try it next week.

    > Try using a larger value for K and RBD. Just make sure RBD never exceeds the K value.
    We increased the value of K and RBD (K=10 - old value, K=30 - new value), but this did not affect.

    > Does slowing the serdes help any?
    We have reduced the speed by half, but the errors remained.

    > The DAC has an option to do eyescan on the individual lanes. Have you tried using this feature?
    Eyescan has not been done yet, we plan to do it next week.


    Best regards

    Evgeniy

  • Feel  free to send the DAC portion of your schematic if you would like us to review it. We can do this off line if needed.

  • Jim,

    here is DAC38J82 schematic:

    Best regards

    Evgeniy

  • Evgenly,

    When the DAC starts to have this issue, what is the status of the DAC PLL lock (address 0x6c bit 0)? What values are you reading for the PLL LF Voltage (address 0x31 bits 2:0) and the VCO tune value (address 0x33 bits 14:9)? The PLL may be going out of lock at this temp due to some settings may be on the edge of the VCO range. What frequency is the VCO set to?

    Regards,

    Jim

  • Jim,

    > When the DAC starts to have this issue, what is the status of the DAC PLL lock (address 0x6c bit 0)?
    DAC PLL is always lock (0x6c bit 0 is equal to zero).

    > What values are you reading for the PLL LF Voltage (address 0x31 bits 2:0) and the VCO tune value (address 0x33 bits 14:9)?
    PLL LF Voltage = 011 and VCO tune value = 110110 (54 dec).

    > What frequency is the VCO set to?
    DAC VCO frequency is 4480 MHz. We use 4GHz VCO (pll_vcosel = 1).

    Best regards

    Evgeniy

  • Evgenly,

    What is the status of serdes PLL in the error state? This is address 0x6C bits 2 and 3. Have you tried the cold spray test yet? Any chance you tried the Eyescan test?

    Regards,

    Jim

  • Jim,

    > What is the status of serdes PLL in the error state?
    0x6C 2 bit is always 1 (when there are errors and when there are none), 0x6C 3 bit is always 0.

    > Have you tried the cold spray test yet?
    Tomorrow we will try to heat separately the FPGA, DAC and synthesizer chips.

    > Any chance you tried the Eyescan test?
    Most likely, we will not be able to do this. Because the JTAG pins were not connected to the FPGA/connector.

    Best regards

    Evgeniy

  • Evgeniy,

    If you have SYSREF continuously running, turn it off after the link has been established.

    Regards,

    Jim

  • Jim,

    Yes, we turn off SYSREF after established link.

    Regards,

    Evgeniy

  • Evgeniy,

    Have you tried leaving SYSREF running the entire time? What setting are you using for the DAC CLK coming from the LMK? LVPECL2000mV? If not, try this.

    Is SYSREF AC or DC coupled?

    Regards,

    Jim

  • Jim

     > Have you tried leaving SYSREF running the entire time?

    We made SYSREF continuous but it had no effect.

     

    > What setting are you using for the DAC CLK coming from the LMK? LVPECL2000mV?

    Yes, DAC CLK and SYSREF are LVPECL 2000mV.

     

    > Is SYSREF AC or DC coupled?

    SYSREF is DC coupled.

     

    We tried cooling the chips separately yesterday. We cooled the DAC, FPGA and synthesizer separately, but this did not affect the JESD errors.

    We noticed one peculiarity. When JESD errors occur with increasing temperature, the frequency of occurrence of 2-3 errors per hour.

    And then if turn off and turn on the power at an high temperature, JESD errors start to go constantly (one error in about 4 seconds).

     

    Best regards

    Evgeniy

  • Evgenly,

    I thought your problem was at cold temps. Can you try using a heated air source that can be applied to one device at a time? Have you measured the amplitude of the CLK going to the DAC at high temp?

    If possible, switch the DAC mode of operation to either a LMF setting of 124 or 222. This will allow you to operate the DAC with only 1 or 2 lanes. If the setup passes, switch the lanes used by the DAC. This way you can isolate each lane to see if the problem is related to a particular lane.  

    Regards,

    Jim

  • Jim,

    Yes, we tried to heated up every device separately but issue is remain. No, we didn't measure amplitude.

    We tried to work with different JESD lines but issue stil remain too.

    Best regards,

    Evgeniy

  • Evgenly,

    What exactly happens when you heat up individual parts? It is not clear by your response. How are the voltage levels on all supplies during failure mode? Are any of the supplies underrated? Can you try running the PRBS test modes at high temp and monitor each lane using the DTEST mode. The results will be on the ALARM pin for these tests. Can you operate the LMK so that DCLK8 is at around 3GHz and use this as the DAC CLK instead of the DAC PLL. This would tell you if the DAC PLL is the issue.

    Regards,

    Jim 

  • Jim,

    there is no differences what component we heated up separately because all components heated up by themselfes after some time working and issue appears. We tried to cool down components separately. No results.

    Voltage levels on all supplies is normal, without underrated. No we didn't run PRBS, thanks, we will try.

    Yes, we tried work without DAC PLL and get clock signal from LMK, it is not solve the issue.

    Best regards,

    Evgeniy

  • Evgenly,

    I would suggest running the PRBS test at the temperature the setup fails. If you see failures, then try adjusting the serdes gain and equalization options the FPGA and DAC has available. If this does not help, start swapping out parts. Maybe you have  a bad unit. I am guessing the issue is the layout of the PCB, a soldering issue, or a possible bad unit. Do you see this issue on all boards?

    Regards,

    Jim  

  • Jim,

    We have 3 boards and all of them has same issue. Suggestion of bad soldering and unit is not confirm. Bad layout may be but we swap JESD lines (they has different paths) and it has no effect.

    Best regards

    Evgeniy

  • If it is bad layout, it could effect all lanes so switching lanes would still have a problem. Are the power supplies dropping in voltage at high temp? Are they capable of providing enough current? Need to see what the PRBS test reports.

  • Jim,

    We find a problem. It is crosstalk issue. We find agressor net, but still don't understand what role temperature playing.

    Best regards

    Evgeniy