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DDC112 first sample wrong after changing range.

Chad Southwell
Prodigy 90 points
Other Parts Discussed in Thread: DDC112

Hi everyone,

After changing the range selection the first conversion result is incorrect ( larger than it should be). Subsequent samples are stable and correct. 

This is true in either test mode or from attached photodiode (dark for now) and I'm running continuous operation

Is the range selection latched on CLK or CONV, or are the range selections immediate?

At this time my noise floor is 12 counts RMS in test mode, range = 5.

Thanks.

Chad Southwell

Photon Kinetics

  • 0
    Prodigy 90 points

    More information....

    I'm running external caps of 270pF. I get the bad first sample when going into range 0 (ext. caps) from any other range. Going from range 0 to any other range the first sample is good.

    Chad

  • 0 in reply to Chad Southwell
    TI__Guru** 113765 points

    Chad,

    I will have to verify with the design group, but I believe the range settings take effect as soon as they are set/changed, but will not change the operation of the system until the next CONV.  I have not tried to do this while in continuous mode on the fly.  The EVM software has two separate actions.  One is to set up the device, and the other is to collect data.

    Test mode does have a setup requirement of 100nS before CONV. 

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 90 points

    Hi Bob,

    For now I've implemented a waste CONV cycle at the start of an acquisition. This occurs only once at the beginning of a free running or averaging acquisition sequence. I probably have a data retrieval bug but I don't see it in my analysis.

    I'm currently getting 7 bins RMS noise on range 5 in test mode and with my photodiode( 1.5pF) in circuit under no light conditions. The noise is 2X  higher then per the data sheet but reasonable for the prototype.

    I've also gated the CONV pulse with CLK on a d-flop.

    We operate the device in two modes: One is free running, providing a continuous stream of conversion results or Second, averaging a programmed  number averages. In both cases the CONV signal is operating at 540Hz. This allows the part to operate in continuous mode and we fetch data as soon as the DVALID line is asserted low. The signal under test is chopped at 270Hz rate. I can program the 'integration window' to be in the most stable portion of the live signal.

    We use the IN2 input, and only the A side integrating capacitors (rising edge of CONV). The B side integration result is ignored. This way a we fetch only 20bits of data and don't have to calibrate for capacitor value differences.

    I am running the CLK at 12MHz. Is this an issue for the DDC112U-ND part?

    Regards,

    Chad

     

  • 0 in reply to Chad Southwell
    TI__Guru** 113765 points

    Chad,

    For the DDC112U the maximum clock rate is 12MHz for CLK and DCLK, so you should be fine unless your clock is actually running a little faster.  The DDC112UK version will actually run up to 15MHz.

    Regarding noise, layout and external sources are the biggest contributor to noise.  On the EVM we have to place a grounded shield around the DDC112 device to get the appropriate noise figures.

    Best regards,

    Bob B