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ADS1231: SPI Communication

Part Number:

Hi team,

My customer is designing a 1 master (Renesas RX651) 3 slaves (ADS1231) serial communication system, could you help answer below questions?

1. Does this ADC supports SPI?

2. If so, can we use PDWN as SS?

3. If PDWN is Low(enabled), DOUT is HI-Z?

4. Besides SPI, Do we need another port for Data-Ready?

5. Could you explain the communication algorithm of ADS1231?

Best,

Zeming

  • Hi Zeming,

    The ADS1231 is a pin configurable device and therefore does not have a DIN pin to use for SPI.  The ADS1231 does use an SPI compatible interface, but what is often confusing is the communication is initiated from the controller by writing to the TX buffer so that SCLKs are transmitted.  So even though there is no input on the ADS1231 to transfer data to, the only way to initiate the SCLKs for retrieving the data is to write bytes to the TX SPI buffer on the micro.

    See my additional comments below.

    Best regards,

    Bob B

    Zeming Kong said:

    Part Number: ADS1231

    Hi team,

    My customer is designing a 1 master (Renesas RX651) 3 slaves (ADS1231) serial communication system, could you help answer below questions?

    1. Does this ADC supports SPI? [Bob] Yes, this device does communicate using the SPI protocol, but there is no CS (SS) pin and the conversion data is transmitted on the DOUT/DRDY pin with the SCLK.  So it is a 2-wire version of SPI. 

    2. If so, can we use PDWN as SS? [Bob] The PDWN pin does hold the ADS1231 in a reset state, but it does not place DOUT/DRDY in a high impedance output state.  Instead, the DOUT/DRDY pin is set high.

    3. If PDWN is Low(enabled), DOUT is HI-Z? [Bob] As just mentioned, the output state is logic high when PDWN is set low.  This is demonstrated in Figure 23 on page 15 of the ADS1231 datasheet.  You will note that when PDWN is low, DOUT/DRDY is indicated logic high.  You cannot directly tie the DOUT/DRDY pins of multiple devices together.  You will need to add some other logic device as well.  One example is to use the SN74LVC1G125 (enable low) or SN74LVC1G126 (enable high) in series with each ADS1231 DOUT/DRDY signal output.  There are also multiple gate packages available as well.

    4. Besides SPI, Do we need another port for Data-Ready? [Bob] There are several methods that can be used to determine when the conversion result is completed.  One method is to poll the status of DOUT/DRDY and another method is to use an interrupt driven system where a transition from high to low triggers an interrupt to start reading the conversion results.  This can be done by either switching the input from SPI to GPIO mode between read cycles or you can connect the DOUT/DRDY to two input connections in parallel where one input is dedicated as a GPIO for detecting end of conversion and the other input as the MISO connection to the SPI bus.

    5. Could you explain the communication algorithm of ADS1231? [Bob] The ADS1231 runs continuously in normal operation.  Once a conversion completes, the DOUT/DRDY will toggle or transition from a logic high to logic low state.  At this time the conversion results should be read from the ADS1231 and the communication completed prior to update of the next conversion completion.  If the next conversion completes and updates before the previous conversion is finished being read from the device, the data will become corrupted.  Sending 24 SCLKs will transmit the entire conversion result.  Sending additional SCLKs will force DOUT/DRDY high.

    Best,

    Zeming

  • Hello Bob,

    Thanks a lot for your comment!

    According to your recommendations, the customer decided to use buffers between MCU and ADCs for DOUT and SCLK communication, and SS is connected to EN of buffers to select slave device.  

    Do we have a open-drain type buffer that can switch 3-state with 1 bit?

    Best,

    Zeming

  • Hi Zeming,

    I am not aware of any open drain buffers with a 3-state enable.  Open drain is usually used in level translation applications where the output is pulled low for logic low or the output is pulled high and becomes the pullup impedance.  Buffers with an enable pin are push-pull outputs where in the disable state places the device into a high impedance output state and in the enable state is driving the output as logic high or logic low.

    It is always possible to connect devices in series for a particular outcome.  For logic device questions I would suggest contacting the logic forum.

    Best regards,

    Bob B

  • Hi Bob,

    Appreciate your explanation!

    I have checked our buffer lineup as well, there seems to be no such open-drain product. So I suggested SN74LVC1G125/126.

    Best,

    Zeming