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ADS62P25: ADS62P25 LVDS level

Part Number: ADS62P25

Dear Team

Good day!

Our customer use the ADS62P25 High speed ADC

He want to interface the LVDS output of the ADC to FPGA.
FPGA am using is Arria 10.
But seeing that the Common mode voltage of the ADC is 1.5V and the common mode voltage of the FPGA is 1.25V.
Will there be any problem if he interface both directly .
In the attachment you can see the LVDS level of the FPGA.



  • Leon,

    I would suggest AC coupling the signals. You may need to also add some biasing resistors based on the specs of the FPGA. There is much info regarding this type of interface on the internet. I would also check wit the FPGA manufacture and data sheet regarding this.