Hi,
Could you please give me advice for Latch signal in below condition?
- Daisy chain connection with four DAC8760
- Enable bling CRC
If Latch signal set to High during sending SPI frame, will DAC output be set to unexpected value?
E.g. Latch signal is set to high at the timing when frame is sent 24bit out of 32bit frame length, what will the output be happen?
Regards,
Nagata.