Hi sir
We are using DAC 5674 which is interfacing with Virtex 5 FPGA.
We have an IP DDS Compiler to generate samples.
We have given external clock 50 MHZ to DAC and as well as FPGA.
output frequency of the samples given is 5 MHZ. 10 samples per sine wave reconstruction.
Now, output of DAC 5674, how much frequency we can expect.
In the blockdiagram of the clock generation circuit, there is Phase frequency detect, please can you say about this.
Here we have given PLL VDD is low
X4 is high.
Please suggest us to solve this.
Thanks
Roja V