I would like to run DAC8830 at 50MHz. The datasheet says minimum setup time (Tsu) is 10ns. Does it mean delay must be 0ns? I guess it needs few ns from SCLK's falling edge to SDI.
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I would like to run DAC8830 at 50MHz. The datasheet says minimum setup time (Tsu) is 10ns. Does it mean delay must be 0ns? I guess it needs few ns from SCLK's falling edge to SDI.
Hello,
The setup time must be 10ns before each rising edge. There is no hold time, so the data can change after the rising edge. This means the 10ns high time and the 10ns low time of the SCLK are available for the next rising edge's setup time, so there is some room for a delay in the change of data.
If you look at the timing diagram, you see the Tsu is marked to the rising edge, and Tho is marked to the next falling edge. Tho is 0ns, so the data can be changed in that time.
Does this answer your question? Please let us know if you have any further questions.
Best,
Katlynne Jones
Thank you for your helpful reply.
Does it mean the data should be shifted at rising edge? So, DAC8830 does not use ordinary SPI mode 0, I guess.
Best regards,
Hiroyuki Hashimoto
Hi Hashimoto-san,
Data is latched into input register on the rising edge of SCLK, not falling edge. I believe that the SCLK idle state is don't care, meaning that it could be idle high or low. This means SPI mode 0 or 2 should work. Clock polarity can be 0 or 1. Clock phase must be 0.
Best,
Katlynne Jones
Dear Katlynne-san
You mean DAC8830 use only rising edge of SCLK. I got it.
I guess ordinary SPI master shifts data at falling edge in mode 0. But SPI master for DAC8830 should shift at rising edge to guarantee setup time. Is it right?
Best regards,
Hiroyuki Hashimoto
Thank you very much. I understand a master for DAC8830 should shift at rising edge of SCLK.
Best regards,
Hiroyuki Hashimoto
Hi Hashimoto-san,
The master shifts data on the falling edge, and DAC8830 latches data on rising edge. To guarantee setup time the master can shift the data before the falling edge while the SCLK is high. Another way to guarantee the setup time is to slow the clock by a small amount. This way the normal SPI modes can be used.
Best,
Katlynne Jones
Hi Katlynne-san
Thank you for your kind response.
I will try to slow the clock.
I don't know how can the master, which runs at 50MHz, shift before the falling edge. The master should run at 100MHz or more?
Best regards,
Hiroyuki Hashimoto
Hi Hashimoto-san,
With the built in SPI modes, I don't think there is a way to shift the data before the falling edge. The best solution here to guarantee the setup time would be to slow the clock to add a few ns of error.
Best,
Katlynne Jones
Hi Katlynne-san
Thank you. I appreciate your kindness.
Best regards,
Hiroyuki Hashimoto