ADS1675: The DRDY signal is losed

Part Number: ADS1675


    I am using the ADS1675 in WIDE-BANDWIDTH FILTER mode. I set the START PIN to high for continuous samp. I can see the DRDY pulse and the date out is correct. But , when outside of the board have EMI NOISE such as ESD in the air, the DRDY pulse is losed .The DRDY PIN and the DATA  keep low. At this time , I can see the START PIN is keep high. If I do nothing ,this state will be continue . If  I clear the START PIN to low and then set to hige ,the DRDY can see again ,and the samp data is correct again.

    On my board have other chip ,such as DSP 、FPGA and so on,they are work good always.


  • Hello,

    I do not see anything in your schematic that would cause the ADC to stop working and require a power cycle or reset.  This is likely a board layout issue.

    Can you provide a picture of the board layout, showing the ADC and supply bypass capacitors?

    You mention ESD event; you may need additional protection depending on the path of the ESD current.  Adding a TVS diode to the supply rails, 3VA, +5V, may also help.  The following TI Precision Labs series discusses different protection options.

    Keith Nicholas
    Precision ADC Applications

  • Hi,Keith

        Thank you. Here is the  board layout.

  • Hello Sam,

    Your board layout looks good.  I was concerned about the placement of the power supply bypass capacitors, but you have them directly beneath the device, with a solid ground plane for the entire circuit, which should work very well.

    Here are a couple of suggestions for other possible problem areas:

    1.  A clean clock is very important for good operation, and if it glitches due to an ESD event, this could be part of the problem.  Looking at your layout, it looks like you have it routed on the inner 'green' layer, and it appears to be running to more than one device.  You may want to try adding a small filter to the pin.  Adding a series 50ohm resistor will work with the pin capacitance to provide a simple RC filter that may help.  I am not certain how best to modify your board, but you could lift the CLK pin 55 and add the resistor between the chip pin and the board pad.  Also, the CLK input is powered from the analog domain of the ADS1675, and must be driven with a clock source relative to AVDD; in your case a 5V CMOS square wave clock source.  

    Can you confirm the amplitude of your CLK source?

    2.  The START pin controls the operation of the device, and if this pin glitches due to an ESD event, it could cause the part to stop working correctly.  A similar suggestion, you may want to add a small RC filter to this pin as well in case there is any ESD energy coupling into this input.  A 50ohm series resistor and 10pF input capacitor should help.


  • Hello Keit,

    Thanks a lot.

        I add a 50ohm resistor between PIN55 and the board,add a RC filter to the START pin,but the problem still existent.

       On my board ,there are four ADS1675 works together. So, the CLK 、START are connect to the four ADS1675。The CLK 、START are from FPGA which is DGND area . ADS1675 and other analog circuit are in AGND area . I find the ADCs at periphery of the AGND area are stop  easier ,such as ADC 1 and 4. And the ADCs 2 and 3 srop fewer.

    Can I have some more advice?

    Thanks again.

  • Hello Sam,

    You state:The CLK 、START are from FPGA which is DGND area . ADS1675 and other analog circuit are in AGND area .

    Based on your description, you have two separate ground planes: AGND and DGND.  These must be connected together with a low impedance connection, otherwise, during an ESD event, the two ground planes can have different voltage levels which can cause digital communications to fail.

    How do you connect DGND and AGND together on the board, and what location?  Can you show a picture of the board layout that shows both AGND and DGND, as well as the connection between the two grounds?


  • Hello Keith,

        Here is my whole board . Between the AGND and DGND , I use a common mode choke . I remove the common mode choke for test . And connect the two side direct  . Then I find  the problem become fewer .

        So, how can I do better?


  • Hello Sam,

    Removing the common mode choke between AGND and DGND should help, but you still have a long path for the digital ground currents.  The best place to connect the AGND and DGND planes together is the location where the digital control lines cross between the two grounds.

    I am not sure how you can modify your existing board, but connecting the two grounds at the location below should significantly reduce or eliminate the ADC communications errors.


  • Hello Keith,

        OK, I will modify the layout latter.

    Thank you !!!

  • Hello Sam,

    You are welcome!