ADS54J69: ADS54J69: Sampling Rate Minimum

Hello,

We have an application where we'd like to operate the ADS54J69 at a rate below 250MSPS, but the datasheet seems to imply that the device is not capable of using an input clock of less than 500 MHz (section 7.3). However, there is another post on the E2E forum that suggests the minimum sampling rate is really driven by the minimum serdes rate of 2.5Gbps

(+) ADS54J69: minimum device clock frequency - Data converters forum - Data converters - TI E2E support forums

That said, would it be possible to run the ADS54J69 with an input clock of 409.6MHz and achieve a JESD(LMFS=2242) ADC output rate of 204.8MSPS @ 4.096 Gbps lane rate? From the referenced post, I would assume this is possible but wanted to confirm.

Thank You,
David