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ADC12D1620QML-SP: Cut down on the amount of parallel pins

May
Genius 9880 points
Part Number: ADC12D1620QML-SP

Hi Team,

Customer has question regarding ADC12D1620QML-SP. Below is the inquiry.

"

In terms of output modes, it appears that there are I and Q outputs, is there a mode where we can use only I and it will contain all the data?

Is this how the Q Power-down mode works? We're trying to cut down on the amount of parallel pins used to output digitized data but want to use this part, or something in its frequency range.

We're using them in some form of Dual Channel mode.

"

Regards,

Maynard

  • 0
    TI__Genius 9880 points

    Hi Team,

    Any update on this.

    Regards,

    Maynard

  • 0 in reply to May
    TI__Mastermind 20090 points

    Hi Maynard,

    Please let us know the following and we should be able to better help answer your question.

    What is the sampling rate that you plan to use?

    How many analog input channels do you plan to use? (DES single channel? or nonDES dual channel?)

    How many parallel digital output pins are you limited to?

    Regards,

    Rob

  • 0
    Prodigy 10 points

    Hi Rob, we're using two input channels per ADC so it will be a Dual Channel Mode. Sample rate will be less than 800 MSPS. We're interfacing with a Xilinx Virtex Ultrascale+ FPGA, which has performance we are looking for but still less than 400 differential IOs to utilize. After Flash and other functions we are out of pins assuming we use two ADCs. We are wanting to explore a 'non-Demuxed' output option if possible with this part.

  • 0 in reply to Milton Watts
    TI__Mastermind 20541 points

    Hi Milton,

    The best option for picking lowest number of data pins is using Non Demux 1:1 mode( selected by setting the NDM to high). With this mode you will be able to send data for I and Q channel over total of 24 pairs of data lines. 

    Regards,

    Neeraj