Open LDI deserializer

thanks! i will try to use the MAP tool according to the attachments, another small related question:

the CML port is not available to test the signal when the data rate is becoming higher? i find that the jitter is more serious when data rate is more higher.

the PLL setting is: Type II -- Loop BW; damping = 2; CR BW = pclk/15MHz.

because we have tested CML port's signal under 1.4Gbps, 2.2Gbps and 3.4Gbps, the jitter is becoming more and more larger, but using the same setting on FPD LINK, will not get such large jitter in signals.

provide this CML test picture, let you understand well for my question.

so due to this physics of CML OUT, it can not be used in my current test during higher frequency, can i understand that? 

No, This is not the case.

You can use CMLOUT for any datarate, but what I wanted to say, is once you increase the frequency it becomes more sensitive to jitter. So this is not the physics of CMLOUT itself, but the High Frequency.

Buttom line, If you see more jitter on CMLOUT that means your signal is jittery. If you measure it using CMLOUT or you measure it directly on the cable, you will see same behaviour.

thanks for your information about CML PORT, i also noticed this difference between CMLOUT0 and CMLOUT1 in measurement;

and you are right, 100MHz is invalid for 948, i will correct this point in test;

but for the jitter, i'm sorry my description wasn't clear enough, actually, i have measured on CMLOUT and directly on the cable, but find the obvious difference;

sharing the below pictures which are the test results of cable, without regard to the bandwidth limitation of equipment, can know that:

1) CMLOUT can't get the same performance at the same setting;

2) 948 chip is playing an important role except cable's impaction;

3) PCB routing can almost no impact on it.

based on these results, that's why i have this concern for CMLPORT in test.

ok, your comment keeps the same with my assumption on the CMLPORT isn't the real signal, i think it's clear for me, thanks!

we are more focus on the original signal, so my last question is:

because we just only can measure the DES signal on the pins of 948, the impaction of internally circuiteries and block to equalize can be observed directly?  i'm always thinking this effect can't be observed outside the chip, please kindly correct my view!