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ADS1278-SP: Differences between CLKDIV 0 and 1 in low-speed mode

Kannan Sockalingam
Intellectual 1490 points
Part Number: ADS1278-SP

Hi, am working with a customer on this device. They are operating with a FCLCK of 5MHz (and CLKDIV=0). Unfortunately they have to derate to 80% to meet their spec, so the Max 5.4Mhz x 0.8 is 4.3MHz. They may have to change to the CLKDIV=1, which has a Max FCLK of 27MHz. What happens when they still continue to run at 5Mhz operation with CLKDIV=1? Does the internal timing etc look the same between CLKDIV 0 and 1 since the operating frequency remains at 5MHz?

Thanks in advance.  

  • 0
    Prodigy 10 points

    Question:

    1. whether 27 MHz maximum fCLK during Low-Speed mode can be used regardless of whether the CLKDIV pin is 1 or 0 (i.e. whether the silicon pathways for CLKDIV=0 and =1 are similar enough that the ADC’s internal timing parameters are governed by fCLK = 27 MHz), thus allowing 5 MHz not to violate the frequency derating.
  • +1 in reply to James Valderrama
    TI__Mastermind 36150 points

    Hello James,

    In low speed mode, the ADC modulator bias currents are reduced to optimize for lower power.  This places an upper limit on the CLK frequency to maintain datasheet specifications.  Referring to Table 4, CLKDIV=1 divides the clock by 40, which sets the upper modulator frequency to 27MHz/40=675kHz.  If using CLKDIV=0, the maximum CLK frequency is now 5.4MHz, which results in the same maximum modulator frequency of 5.4MHz/8=675kHz.

    If you operate in Low-Speed mode with CLK=5MHz and CLKDIV=1, your output data rate will be 20% (1/5th) verses CLKDIV=0.  Table 5 shows the relationship between CLK and output data rate.

    Regards,
    Keith Nicholas
    Precision ADC Applications