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how to configure the AIC3204's sampling rate at 192K without using the C filter?

Kieran Yu
Intellectual 525 points
Other Parts Discussed in Thread: TLV320AIC3204

recenltly, i want to configure the ADC sampling rate to be 192Kz, but i 'm in trouble wth that. it doesn't configure right. is there any tips on how to configure the sampling to 192K, the datasheet just uses the 48K as introduction. by the way, when i configure the sampling rate at 192K, but i don't want to use the C filter, how can i configure the sampling rate at 192K and don't use the C filter? or they are like twins that you can't separate them ?

 thanks in advance

  • 0
    Expert 1215 points

    CODECs section would be better place for that question. I suppose you are not forced to use decimation filter, but since oversampling is essential for ADC work, it must be used to make audio stream correct.

    regards

    MS

  • 0
    TI__Mastermind 30140 points

    FYI - I moved your post to the Audio Converters forum where they can address your AIC3204 CODEC questions.

    Regards,
    Mark

  • 0 in reply to Mark M
    Intellectual 525 points

    hi MS

           so the decimation filter must be used, chosing among A filter, B filter and C filter.  "The TLV320AIC3204 offers 3 different types of decimation filters. The integrated digital decimation filter removes high-frequency content and down samples the audio data from an initial sampling rate of AOSR*Fs to the final output sampling rate of Fs. The decimation filtering is achieved using a higher-order CIC filter followed by linear-phase FIR filters. The decimation filter cannot be chosen by itself, it is implicitly set through the chosen processing block."

            my input signal's center frequency is 40Kz with bandwidth of + - 2.5Kz,  so want  to configure the AIC3204's sampling rate at 192Kz, and i also see  "Filter type C along with AOSR of 32 is specially designed for 192ksps operation for the ADC. The pass band which extends up to 0.11*Fs ( corresponds to 21kHz), is suited for audio applications."  if that so,   the pass band is below 40Kz, my useful signal will be filtered away. that's not i wanted. so want to know how to configure the codec, satisfing not only sampling rate at 192Kz,but also can make sure 40Kz signal pass ?

    thanks in advance

  • 0
    TI__Mastermind 46195 points

    Hello Kieran,

    Filter C is only compatible with an AOSR of 32. Similarly, Filter B is only compatible with an AOSR of 64.

    Using an AOSR = 32 and Filter B will result in a gain error of -24dB. This gain error occurs in a section of high resolution of the processing engine in which most LSBs are preserved after the attenuation. This means that if we apply 24 dB in the digital domain (ADC digital gain) the SNR will not suffer 24dB of degradation.

    In AIC3254, the fix is easy. You can use a shift scale component to compensate in the miniDSP.

    In AIC3204 the maximum digital gain is 20dB. If you are OK with -4dB gain error, you can just use this gain. If you would like exactly 24dB gain, you can use 20dB in digital PGA and set one biquad as follows:

    N0 = 0

    N1 = 0x656EE3 <- +4dB gain

    N2, D1, D2 = 0

    This will introduce a delay of one sample.

    Page 8 and 9 of the attached pdf shows the performance after the 24dB gain is applied on either PRB or miniDSP mode.

    Regards,

    J-

    1348.AIC3254_4x2x_192ksps_Setup.zip

  • 0 in reply to J-
    Intellectual 525 points

    hello J Arbona

         firstly, thanks for your attached pdf resource, in the pdf file, i saw a graph of 80kHz tone FFT, dese this mean that the frequency over 20Khz dosen't filter away by C filter ? casue i see in the datasheet   "Filter type C along with AOSR of 32 is specially designed for 192ksps operation for the ADC. The pass band which extends up to 0.11*Fs ( corresponds to 21kHz), is suited for audio applications." 

         secondly, you mentioned AOSR =32 and filter B, i am not quite sure about this, can you give some more details ? cause in the datasheet, at the  ADC processing bolcks, it doesn't show the combination of AOSR =32 with filter B, i will apprecaite if you can give more explations.

         my hardware is C5515 USB Stick,  it  has AIC3204 codec included, so i think i can only use the PRB of ADC's and DAC's to configure the dest configuration of 192KHz sampling rate.

          the signal processing  is, first  sampling the ultrasonic signal in 40KHz with 5 bandwidth, i wish i can do this sampling task by the IAC3204's ADC,  then pass the sampled signal to the DSP by the I2S to do frequency decimation.(heterodyning ), after that i wll do bandpass filter, then ouput  the signal processed to the AIC3204's DAC by I2S interface,   then play the signal to the headphone.  

    the most important thing is weather can i use the AIC3204's 192KHz sampling rate to sample my 40KHz signal without filtering away by the inherent  C Filter ? or how can i save my 40Khz signal by what kind of configurations ofAIC3204 ?    and what should i give more considerations when i configure the AIC3204 to my goal configuration ?

    thanks

  • 0 in reply to Kieran Yu
    TI__Mastermind 46195 points

    Hello Kieran,

    "i saw a graph of 80kHz tone FFT, dese this mean that the frequency over 20Khz dosen't filter away by C filter"

    - This is using Filter B with AOSR=32. As mentioned previously, the only side effect will be the -24dB gain error.

    Regards,

    J-

     

  • 0 in reply to J-
    Intellectual 525 points

    thanks for your patience and help, english is not my first language, there is some misunderstanding.  i will try to configure the AIC3204 to be FilterB and AoSR = 32

    thanks agaign

  • 0 in reply to Kieran Yu
    Intellectual 525 points

    hello 

    i'm tring to configure the AIC3204 to be AOSR =32 and use B filter with sampling rate of 192KHz ,however, it 's always mute. i check it out for twice. i must  configure some registers wrongly.


     ;****************************************************************************************
    ;   brief description:
    ;  1、using PLL:codec_clock<-PLL_colck; PLL_in_cloc<-MCLK
    ;  2、power supply mode:
    ;  3、choosing B filter for ADC and DAC
    ;  4、both AOSR and DOSR are equal to 32
    ;  5、the sampling rate is 192Khz for ADC and DAC
    ;
    ;  the following code is for configure the AIC3204 at 192KHz sampling rate with B
    ;  filter(cause the C filter will bring out a cutoff frequency at about 20KHz)by
    ;  inherent decimation filter(this filter is for oversapmling and filter away the
    ;  high frequency content),the side effect of this configuration with connection B
    ;  filter with AOSR = 32 is that it will lead to 24dB's degradetion. and this can
    ;  be compensated by ADC digtal control with 20dB added.

    ; time history:
    ;  2011-5-20 created
    ;  2011-5-
    ;****************************************************************************************


    ;****************************************************************************************
    ; configure software reset
    ;****************************************************************************************
     ;select page 0
     AC1 = 0x00
     AR1 = 0x00
     call i2c_WriteData8
     ;software reset
     AC1 = 0x01
     AR1 = 0x01
     call i2c_WriteData8

    ;****************************************************************************************
    ; configure power supply mode,program PLL clock and power up
    ; 1、MCLK = 12M, CODEC_CLK = 12*8.9120=98.304M
    ; 2、ADC_Fs = DAC_Fs = 98.304/2/8/32 = 192KHz
    ;****************************************************************************************
     ;/* still in page 0 */
     ;MCLK->PLL_IN_CLK PLL_CLK->CODEC_CLK
     AC1 = 0x04
     AR1 = 0x03
     call i2c_WriteData8
     ;P = R = 1 and power up PLL
     AC1 = 0x05
     AR1 = 0x91
     call i2c_WriteData8
     ;J = 8
     AC1 = 0x06
     AR1 = 0x08
     call i2c_WriteData8
     ;D = 1920 = 0x0780; write MSB(0x07)
     AC1 = 0x07
     AR1 = 0x07
     call i2c_WriteData8
     ;write LSB(0x80)
     AC1 = 0x08
     AR1 = 0x80
     call i2c_WriteData8
     
    ;****************************************************************************************
    ; configure BLCK and WLCK mode、 audio interface mode、 data word length、BLCK divider
    ;****************************************************************************************
     ;/* still in page 0 */
     ;set BLCK and WCLK as output; audio ininterface = I2S; data word length = 16bits
     AC1 = 0x1b  ;page 0 register 27
     AR1 = 0x0d
     call i2c_WriteData8
     ;power up, BLCK N diviver = 8
     AC1 = 0x1e
     AR1 = 0x88
     call i2c_WriteData8
     
    ;****************************************************************************************
    ; program and power up NADC and NDAC, MADC and MDAC, AOSR and DOSR
    ;****************************************************************************************
     ;/* still in page 0 */
     ;power up NDAC divider and NDAC = 2
     AC1 = 0x0b
     AR1 = 0x82
     call i2c_WriteData8
     ;power up MDAC divider and MDAC = 8
     AC1 = 0x0c
     AR1 = 0x88
     call i2c_WriteData8
     ;DOSA = 32
     AC1 = 0x0d
     AR1 = 0x00 ;MSB
     call i2c_WriteData8
     AC1 = 0x0e
     AR1 = 0x20 ;LSB
     call i2c_WriteData8
     
     ;power up NADC = 2
     AC1 = 0x12
     AR1 = 0x82
     call i2c_WriteData8
     ;power up MADC = 8
     AC1 = 0x13
     AR1 = 0x88
     call i2c_WriteData8
     ;AOSR = 32
     AC1 = 0x14
     AR1 = 0x20
     call i2c_WriteData8

    ;****************************************************************************************
    ; progaram the processing block for ADC and DAC(if needed)
    ;****************************************************************************************
     ;/* still in page 0 */
     ;ADC choosing PRB_R7, using B filter
     AC1 = 0x3c
     AR1 = 0x07
     call i2c_WriteData8
     ;DAC choosing PRB_R7,using B filter
     AC1 = 0x3d
     AR1 = 0x07
     call i2c_WriteData8

    ;****************************************************************************************
    ; disable coarse AVdd generation
    ;****************************************************************************************
     ;/* change to page 1 */
     AC1 = 0x00
     AR1 = 0x01
     call i2c_WriteData8
     ; disable weak connection of AVDD with DVDD
     AC1 = 0x01
     AR1 = 0x08
     call i2c_WriteData8

    ;****************************************************************************************
    ; enable Master Analog Power Control
    ;****************************************************************************************
     ;/* in page 1 */
     ;enable Analog Bolcks and LDO
     AC1 = 0x02
     AR1 = 0x01
     call i2c_WriteData8

    ;****************************************************************************************
    ; program Common Mode voltage(using default)
    ;****************************************************************************************
     ;/* in page 1 */
     ;AC1 = 0x0a
     ;AR1 = 0x00
     ;call i2c_WriteData8

    ;****************************************************************************************
    ; program PowerTune(PTM)(using the default PTM3/4)
    ;****************************************************************************************
     ;/* in page 1 */
     ;left DAC
     ;AC1 = 0x03
     ;AR1 = 0x00
     ;call i2c_WriteData8
     ;right DAC
     ;AC1 = 0x04
     ;AR1 = 0x00
     ;call i2c_WriteData8

    ;****************************************************************************************
    ; program MicPGA startup delay
    ;****************************************************************************************
     ;/* in page 1 */
     ; startup delay 3.1 ms
     AC1 = 0x47
     AR1 = 0x31
     call i2c_WriteData8

    ;****************************************************************************************
    ; program Reference fast charging
    ;****************************************************************************************
     ;/* in page 1 */
     ;charging time to 40 ms
     AC1 = 0x7b
     AR1 = 0x01
     call i2c_WriteData8

    ;****************************************************************************************
    ; Routing of inputs/commom mode to ADC input and Routing of DAC output to the output amplifier
    ;****************************************************************************************
     ;/* in page 1 */
     ;left channel DAC is routed to HPL
     AC1 = 0x0c
     AR1 = 0x08
     call i2c_WriteData8
     ;right channel DAC is routd to HPR
     AC1 = 0x0d
     AR1 = 0x08
     call i2c_WriteData8
     
     ;IN2_L to LADC_P through 20 kohm means 0dB衰减
     AC1 = 0x34  ;page 0 register 52
     AR1 = 0x10
     call i2c_WriteData8
     ;IN2_R to RADC_P though 20 kohm means 0dB衰减
     AC1 = 0x37  ;page 0 register 57
     AR1 = 0x10
     call i2c_WriteData8
     ;CM_1 (common mode) to LADC_M though 20 kohm
     AC1 = 0x36  ;page 0 register 54
     AR1 = 0x01
     call i2c_WriteData8
     ;CM_1 to RADC_M through 20 kohm
     AC1 = 0x39  ;page 0 register 57
     AR1 = 0x01
     call i2c_WriteData8
     ;unmute MicPGA_L
     AC1 = 0x3b
     AR1 = 0x00
     call i2c_WriteData8
     ;unmute MicPGA_R
     AC1 = 0x3c
     AR1 = 0x00
     call i2c_WriteData8 
     
    ;****************************************************************************************
    ; unmute analog PGAs and set analog gain; unmute and set gain of output driver;
    ; volume control; power up output driver
    ;****************************************************************************************
     ;/* change to page 0 */
     AC1 = 0x00
     AR1 = 0x00
     call i2c_WriteData8
     ;left ADC channel volume = +20dB
     AC1 = 0x53 ;page 0 register 83
     AR1 = 0x28
     call i2c_WriteData8
     ;right ADC channel volume = +20dB
     AC1 = 0x54 ;page 0 register 84
     AR1 = 0x28
     call i2c_WriteData8
      
     ;DAC left and right channel unmute,left control right volume
     AC1 = 0x40  ;page 0 reigster 64
     AR1 = 0x0e
     call i2c_WriteData8
       
     ;/* change to page 1 */
     AC1 = 0x00
     AR1 = 0x01
     call i2c_WriteData8
     ;unmute HPL, +28dB gain
     AC1 = 0x10  ;page 1 register 16
     AR1 = 0x1c
     call i2c_WriteData8
     ;unmute HPR, +28db gain
     AC1 = 0x11  ;page 1 register 17
     AR1 = 0x1c
     call i2c_WriteData8
     
    ;****************************************************************************************
    ; Power up ADC and DAC
    ;****************************************************************************************
     ;/* change to page 1 */
     AC1 = 0x00
     AR1 = 0x01
     call i2c_WriteData8
     ;power up HPL and HPR
     AC1 = 0x09
     AR1 = 0x30
     ;/* change back to page 0 */
     AC1 = 0x00
     AR1 = 0x00
     call i2c_WriteData8
     ;power up left and right ADC channel
     AC1 = 0x51 ;page 0 register 81
     AR1 = 0xc0
     call i2c_WriteData8
     ;unmute left and right ADC channel
     AC1 = 0x52 ;page 0 rgister 82
     AR1 = 0x00
     call i2c_WriteData8
     
     ;power up left and right DAC channel
     AC1 = 0x3f ;page 0 register 63
     AR1 = 0xd4
     call i2c_WriteData8
     
    ;****************************************************************************************

  • 0 in reply to Kieran Yu
    Prodigy 30 points
    Hi Kieran Yu
    I am attempting to do a very similar project to you, however, I am using the C5535ezdsp board but it uses the same AIC3204 chip. I noticed the reason your output was muted is because you set your register 64 on page 0 to mute the ADC. I set mine as below and it seems to output.
      ;DAC left and right channel unmute,left control right volume 
        AC1 = 0x40  ;page 0 reigster 64
        AR1 = 0x02 
        call i2c_WriteData8
    I am however still having problems getting it to work with high frequency signals (I'm operating at 30kHz), and reading in data straight into the DMA through the i2s. Would be very interested to know how your project went on.
    Dan