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AIC3101 Dual Rate

KANJI SHIBATANI
Mastermind 6205 points

 

Hello, Would you please lt me know about Q1 & Q2 about AIC3101 dual rate?

I can not find any description is the D/S.

QUESTIONs

 ( please refer to  AIC3101 data sheet page 28 and page 30)

Q1  AIC3101 Dual rate enable/desable is NOT available  when using CLKDIV?( We think so)

Q2  CODEC_CLK  must be 256 x fs ?  ( We think so)

 

BackGround

 

My customer use AIC3101 for audio recording and mass production should be soon. 

Customer want to use AIC3101 under WCLK= 96KHz. ( hope freq responce 20Hz~ 40KHz) .

Other conditoin is following

/slave mode

/ use CLKDIV

/BCLK=64Fs =6.144MHz ( applied from external)

/Q=2

-------------------------------

"" Case 1 MCLK=128Fs=12.288MHｚ ""


・CLKDIV  Q=2


・WCLK=1Fs=96kHz、BCLK=64Fs=6.144MHｚ Slave

・DUAL RATE MODE enable

==>>> No output found

Regardless of  ADC/DACのPOWER Up/Down setting

 

"" Case 2   MCLK=256Fs=24.576MHｚ""

DUAL RATE MODE enable

Other setting is same as case1

==>>> works fine. freq responce 20Hz~40KHz almost flat.

"" Case 3 using PLL ""

・MCLK=128Fs=12.288MHｚ


・K=1.0　　R=8　　P=1


・WCLK=1Fs=96kHz、BCLK=64Fs=6.144MHｚ

・DUAL RATE MODE enable

==>>> works fine. freq responce 20Hz~40KHz almost flat.

  • 0
    TI__Mastermind 28585 points

    I will have to do some research on this. I will come back with an answer shortly.

     

     

  • 0
    TI__Mastermind 28585 points

    Shibatani-san,

    I think the issue is explained on the bottom of Page 35 of AIC3101 data sheet. Although the data sheet only mentions the DAC this is true for the ADC and DAC. When Dual Rate is used, Q must be 4, 8, 9, 12, 16. If other values are needed then PLL can be used.

     

    So in case 1, Q must not be 2.

     

     

  • 0 in reply to Converter Apps
    Mastermind 6205 points


    Hello,

    Thank you for your answer.

    Customer use AIC3101 for portable audio recorder and  they decided to use under PLL _IN mode.

    ( Csutomer had tried as per your advise  24.576MHz input ,Q=4 , Dual rate enable, but  output sometimes stopped....

    and he gave up CLK_DIV mode under 96KHz)

     

    Here is additional question.

    Cusomter's condition is below.

    . clock slave ( I2S clock applied from externally)

    . MCLK=12.288MHz

    . PLL mode

    . K=1,R=8,P=1,  ( so, fs(ref) is 48KHz.)

     WCLK 48KHz Or 96KHz ( dual rate desable/enable )

    Q1 

     In order to change the WCLK (48K<=>96K) ,just need to set dual rate enable/desable,

    and no need to set the K*R/P value .

     Is this idea correct?

    Q2    ADC/DAC Power On/Off should be necessary?


          Power Off=> dural rate Enable/Desable => Power On for ADC/DAC

    Sorry to bother you again, but customer must fix thi s issue by X'mas.

    Please give us your advise.

    Best Rgards

    Kanji Shibatani

     

  • 0 in reply to KANJI SHIBATANI
    TI__Mastermind 28585 points

    Shibatani-san,

     

    Q1. Yes, If everything is set up for 48 ksps, then only dual rate needs to be set to change to 96 ksps.

     

    Q2. Yes, it is best to power down ADC/DAC when changing sample rates.

     

    Also you mentioned that the output sometimes stops. It is very important when changing sample rate to power down ADC and DAC. Also if PLL is used, PLL must be powered down to change any PLL settings. so the sequence would look like this:

    1.Power down ADC/DAC

    2.Power down PLL

    3.Change PLL settings

    4.Power up PLL

    5.Power up ADC/DAC