TLV320DAC3100: correct WCLK, BCLK and DIN, wrong SPKP/SPKM output

Paul Singh

Hi,

I am trying to make DAC3100 work as a I2S master. After setting page 0 register 0x1D and 0x1E as in http://e2e.ti.com/support/data_converters/audio_converters/f/64/p/191267/686084.aspx#686084, correct WCLK and BCLK output is now observed.

On the CPU side, the MCBSP has also been configured to slave mode (FSX and CLKX as input) and could output data.

I also compared with application note’s TMS320C6000 McBSP: I2S Interface diagram (SPRA595)’s timing diagram:

1. WCLK changes on the falling edge of BCLK

2. Data MSB is delayed one bit after WCLK’s start.

Everything so far has been correct. However on the SPKP and SPKM output (I intend to use speaker rather than headphone), there is only a fixed frequency clock signal observed, but not the actual data (some particular patterns) as on the DX pin. The DX pin’s connection with DAC3100’s DIN pin has also been confirmed to be good.

Some parameters:

1. DAC_fs: 44.1K

2. Word length: 16 bit

The clock signal observed on SPKP/SPKM is around 287K, not even a multiple of DAC_fs, and doesn’t not change no matter what type data pattern is on the DIN pin.

Here is the register setting (BCLK & WCLK output are correct):

register setting said:

uint8_t dac_data;

//page 0

       AIC3106_writeRegister(0x00, 0x00);//page 0

       AIC3106_writeRegister(0x01, 0x01);//? p46: Initiate SW reset (PLL is powered off as part of reset)

       AIC3106_readRegister(0x36, &dac_data);

       dac_data &= ~0x06;

       dac_data |= 0x02;

       AIC3106_writeRegister(0x36, dac_data);//enable DIN, though not necessary since it is by default enabled

       AIC3106_writeRegister(0x1b, 0x3c);//I2S, both BCLK and WCLK output

       AIC3106_writeRegister(0x04, 0x03);//Clock-Gen Muxing: MCLK -> PLL, PLL -> CODEC

       AIC3106_writeRegister(0x06, 0x07);//J=7

       AIC3106_writeRegister(0x07, 0x02);//D MSB 512

       AIC3106_writeRegister(0x08, 0x30);//D LSB 48

       AIC3106_writeRegister(0x05, 0x91);//PLL on, P=R=1

       USTIMER_delay(12000); //delay 12ms > 10ms

       AIC3106_writeRegister(0x0b, 0x85);//NDAC on, 5

       AIC3106_writeRegister(0x0c, 0x83);//MDAC on, 3

       AIC3106_writeRegister(0x0d, 0x00);//DOSR MSB 0

       AIC3106_writeRegister(0x0e, 0x80);//DOSR LSB 128

       AIC3106_writeRegister(0x3f, 0xd4);//Left & right DAC on, and select data path

       AIC3106_writeRegister(0x40, 0x00);//left & right DAC not muted

       AIC3106_writeRegister(0x3c, 0x0b);//PRB_P11, stereo

       AIC3106_writeRegister(0x1d, /*0x05*/0x01);//BCLK and WCLK Active Even With Codec Powered Down

                                                              //BDIV_CLKIN = DAC_MOD_CLK = DOSR * DAC_fs

       AIC3106_writeRegister(0x1e, 0x84);//Divider on, /4

//page 1

       AIC3106_writeRegister(0x00, 0x01);//page 1

       AIC3106_writeRegister(0x20, 0x86);//Class-D output driver is powered up

       AIC3106_writeRegister(0x2a, 0x05);//Class-D driver is not muted.

       AIC3106_writeRegister(0x23, 0x44);//DAC_L is routed to the left-channel mixer amplifier

                                                               //DAC_R is routed to the right-channel mixer amplifier

What should I do in order to get correct data output on SPKP/SPKM?

Paul

over 13 years ago

0 Vins over 13 years ago

TI__Expert 4840 points

Paul, the channel is not complete yet. Route the left mixer to class D.

P1/R38

0 Paul Singh over 13 years ago in reply to Vins

Expert 2750 points

Vins,

//page 1

DAC3100_writeRegister(0x23, 0x44);

DAC3100_writeRegister(0x25, 0xff);
DAC3100_writeRegister(0x26, 0xff);

both 37(0x25) and 38(0x26) has been routed. Additionally, in 35(0x23) the DAC_L and DAC_R are also routed to the respective mixer amplifier.

The output on SPKP pin is like below:

The 297.8KHz output frequency is 6.75 times 44.1KHz, not an integer multiple, nor an integer multiple of BCLK.

I wonder does it have anything to do with 5.7.2 "Primary and Secondary Digital Audio Interface Selection"?

0 Paul Singh over 13 years ago in reply to Vins

Expert 2750 points

Vins,

I have not yet plugged a speaker to SPKP/SPKM pins but only measuring SPKP voltage using oscilloscope probes. Does DAC3100 detects presence of the speaker, and when not finding it then gives only clock-like outputs?

0 Vins over 13 years ago in reply to Paul Singh

TI__Expert 4840 points

Paul,

The class D output is in digital format and the frequency will be fixed and outputs will be in phase on both P and M outputs. When a signal is playing correctly, you should see that the frequency is varying. It is not possible to perceive the audio by looking at the signal, better to use speaker.

Use the below script as reference to correct any errors you may have. It appears that the analog volume control is muted in your script.

##########################################
# Configure Class-D Output
##########################################
#
# Switch to Page 1
w 30 00 01
#
# Unmute Class-D (6dB)
w 30 2a 04
#
# Power-up Class-D driver
w 30 20 86
#
# Route Analog Volume Control to Class-D Driver, Muted
w 30 26 FF
#
##########################################

##########################################
# Configure DAC Channel
##########################################
#
# Switch to Page 1
w 30 00 01
#
# DACs routed to Mixer Amplifiers
w 30 23 40
#
# Route Analog Volume Control to Class-D Driver, -30dB
w 30 26 BC
#
# Switch to Page 0
w 30 00 00
#
# Powerup DACs, soft stepping enabled
w 30 3f 94
#
# Unmute DAC, 0dB
w 30 40 04
#
# Switch to Page 1
w 30 00 01
#
# Unmute Class-D (24dB)
# w 30 2a 1c
#
# Route Analog Volume Control to Class-D Driver, 0dB
w 30 26 80
##########################################

0 Paul Singh over 13 years ago in reply to Vins

Expert 2750 points

Vins,

I tested with your register settings but still get the square wave output. A bit frustrating.

Could you provide a full script of the setting up for 44.1KHz I2S mono speaker output, with DAC3100 as master?

Paul

0 Vins over 13 years ago in reply to Paul Singh

TI__Expert 4840 points

Paul,

Attached script that works with TI EVM.

Fullscreen 0488.Speaker_44100.txt Download

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 11.2896MHz,
# WCLK = 44.10 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL_clkin = BCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=8, D=0000
w 30 04 03 91 08 00 00
#
# NDAC = 8, MDAC = 2, dividers powered on
w 30 0b 88 82
#
# DOSR = 128
w 30 0D 00 80
#
###############################################

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P3
w 30 3c 03
#
###############################################

##########################################
# Configure Class-D Output
##########################################
#
# Switch to Page 1
w 30 00 01
#
# class D power up delay for PLL and other blocks settling
w 30 22 70
#
# Power-up Class-D driver
w 30 20 86
#
# Unmute Class-D (6dB)
w 30 2a 04
#
# Route Analog Volume Control to Class-D Driver, Muted
w 30 26 FF
#
##########################################

##########################################
# Configure DAC Channel
##########################################
#
# Switch to Page 1
w 30 00 01
#
# DACs routed to Mixer Amplifiers
w 30 23 40
#
# Switch to Page 0
w 30 00 00
#
# Powerup DACs, soft stepping enabled
w 30 3f 94
#
# Unmute DAC, 0dB
w 30 40 04
#
# Switch to Page 1
w 30 00 01
#
# Route Analog Volume Control to Class-D Driver, 0dB
w 30 26 80

0 Paul Singh over 13 years ago in reply to Vins

Expert 2750 points

Vins,

Sorry for the delay. The reason why my DAC3100 didn't produce expected sound in I2S format was because page 0/ Reigster 28 BCLK offset was not set. In MCBSP I configured MSB of data sample to come one bit clock after frame clock, but had not done that in DAC3100 setting. After setting page 0/Register 28 to 0x01 the output was as expected.

Thanks a lot for help.

0 Vins over 13 years ago in reply to Paul Singh

TI__Expert 4840 points

Paul, glad it worked for you. Thanks for letting us know.

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TLV320DAC3100: correct WCLK, BCLK and DIN, wrong SPKP/SPKM output