Please let me know about an ADC sampling rate setup of TLV320ADC3101.
Initial setting:16kHz.
Although he would like to make MCLK=4.096MHz, the following results will be brought if it calculates by PLL Clock Tool.
Please let me know the place mistaken with the following preset values?
P=1
R=1
J=1
D=0
NADC=1
MADC=2
APSR=128
* 24 pages (following) of a datasheet were read and considered.
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When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
512 kHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55
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Thank you for your consideration.
