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Sample Rate Converter SRC4190 with input 32Fs 44.1KHz (16bit) convertig to 64Fs 48KHz (24 bit) output has silent output

Killian OS
Prodigy 160 points

Other Parts Discussed in Thread: SRC4190

Hi,

I have an SRC4190 setup as follows:

MODE[2:0] = 011 : Slave input and Master output RCKI = 256Fs

RCKI = 12.288MHz crystal oscillator

IFMT[2:0] =  001 : 24 bit I2S input format.

OFMT [1:0] = 01 :  I2S output format

OWL[1:0] =  00: 24 bit output format

I have the SRC working correctly for many input formats and sampling rates converting to 48KHz 24 bit I2S Output EXCEPT for 1 format.

44.1KHz 32Fs input does not convert but instead generates a muted output with some dithering LSBs in the output serial data. The RDY pin goes low suggesting that the rate conversion is good. I have a valid 44.1KHz 32Fs data entering the device as the same data works on the amplifier wgen the SRC is externally  bypassed and the data sheet says that BCKI can be 32Fs which is (32x 44.1KHz) = 1.4112MHz.  The I2S incoming data looks compliant with LRCKI and input SD transitioning on a falling edge of BCK. 

 I performed a manual reset, LGRP is zero, BYPASS is disabled, MUTE is disabled. The key here is that the device works for all other formats up to 192KHz sampling rates. When BYPASS is enabled, output clocks are present but the SD output stays low (LSB dithering disappears).

Any idea why 16 bit I2S data at 44.1KHz will not convert up to 48KHz 24 bit data?

While the datasheet input format table describes 24 bit I2S, it also suggests that BCKI can be a s little as 32Fs which would be 16 bits or one BCK per bit.  I assume that this format can accept I2S at 16 bits (32Fs) up to 32 bits (64Fs) and beyond?

  • 0
    TI__Guru* 84915 points
    Hello, Killian,

    My colleague will take a look at this and he will answer as soon as possible.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Mastermind 28120 points
    Hi Killian,

    If the resolution of the input or output changes, you must change IFMT or OWL accordingly.

    Justin
  • 0 in reply to Justin Bohr
    Prodigy 160 points

    Thanks Justin,

    My refined question is therefore as follows:

    I have set the IFMT to "00"  24 bit I2S.

    The datasheet is a little ambiguous in that it says " The audio data word length may be up to 24 bits for I2S and Left

    Justified formats"

    By stating up to 24 bits, does this suggest formats supported including 16 bit I2S as there is no IFMT selection for 16 bits.

    The datasheet also states "In slave mode, BCKI is configured as an input pin, and may operate at rates from 32fS to 128fS, with a minimum of one clock cycle per data bit."

    With both statements, it is reasonable to assume that 16 bit I2S with BCK at 32Fs is supported which is not working for me at the moment.

    PS: Setting OWL to 16 bits with 16 bit I2S input data at 32Fs does not work either,

  • 0 in reply to Killian OS
    TI__Mastermind 28120 points
    Hi Killian,

    Are you testing this on the EVM? What are you using as a mater clock source and at what frequency? I will try to mimic your setup and debug the issue.

    Justin
  • 0 in reply to Justin Bohr
    Prodigy 160 points

    Thanks Justin,

    I am using my own prototype. I have 2 prototypes with the same behaviour.  There is a xilinx PLD that drives the I2S signals into the SRC. The Master Clock is a crystal oscillator at 12.288MHz and is fed to the SR RCKI input.  The I2S source and control signals are originating from a raspberry PI compute module that is in I2S master mode. Its BCK and LRCK are continuous and look good on a scope. 

    However, when playing certain 16 bit 44.1KHz material, the I2S output puts out a 44.1KHz LRCLK, and a BCK at 1.4112Mhz which is 32 times the LRCLK and the data is 16 bit.  When I feed this directly to the TAS5756 integrated amplifer, the output is good. However when fed to the slave input of the SRC, the output of the SRC is muted although the lsbs in the SRC output seem to dither. If I change the BCK to 64Fs, the SRC starts to work.

    I have the SRC in I2S slave on the input and I2S master on the output as previously described. The PLD is there to route I2S buses and can also externally bypass the SRC which is why I suspect that the SRC does not like 32Fs 16 bit I2S on its input.

    I am not in a position to change the input form to left or right justified audio data as this would require a change to the hardwired pinstrapping and a change to the LInux SoC audio card device driver.

    To recap: input control pins are setup as follows:

    Mode[2:0] = "011"  - Output Port is Master mode with RCKI = 256fS  (RCKI = 12.288MHz to give a 48KHz output sample rate)

    OWL[1:0] = "00"  24 bits although I have tried it at "11" 16 bits with no output either.

    OFMT[1:0] ="01" I2S format

    IFMT[2:0] = "001" - labelled as 24 bit I2S although I suspect this is where the problem is as I am feeding 16 bit at 32Fs.

    Regards,

    Killian

  • 0 in reply to Killian OS
    Prodigy 160 points

    Hi Justin,

    Any update on this?

    My fundamental question is whether a BCK of 32Fs ( one audio data bit per clock) for 16 bit audio at 44.1KHz on the slave input of the SRC is supported when in I2S mode. I have a strong feeling that 64Fs is needed but this is not warned about in the datasheet.. FYI, I tried a drop in replacement from the other firm and it does work in this mode although it is not suitable for my specific application that requires support for input rates of 44.1KHz up to 192KHz.

    Regards,

    Killian

  • 0 in reply to Killian OS
    Prodigy 160 points

    Hi,

    6 weeks gone by without a reply to my simple question.

    Does the SRC4190 support a slave input in I2S mode of 32Fs with one clock per bit at 44.1KHz as described above assuming an MCLK of 12.288MHz?

  • 0 in reply to Killian OS
    TI__Guru* 84915 points
    Hi, Killian,

    I apologize for the late response.

    Effectively, in slave mode, the BCKI may operate at rates from 32fs to 128fs, with a minimum of one clock cycle per data bit.

    Best regards,
    Luis Fernando Rodríguez S.