PCM5142: Device responds twice to a single register read

Hi, Robert,

Thanks for splitting this new question into a different post. The NAK after the second read data indicates that the master device has stopped the communication, so maybe the problem is related to the master device not stopping the communication after the first data read. I would recommend you trying to write something to register 0x3E [different from 0x30] and make the read process depicted again just to check if the second data corresponds to the same or subsequent register.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

This is the result from the write. Clearly some other issues going on here. The corresponding read shows a 0x00, including the double-read situation from before.

It's hard to measure accurately, but I think my rise/fall times are too long. Pushing 1uS 10%-90%. Not sure if that helps. I will use lower pull-up resistors to steepen those waveforms and lessen the bus capacitance on the official version. This is all on a breadboard.

Robert, 

I think your assumption is correct, from the captures sent, it appears the I²C rise and fall time is out of the allowed limits for this device. The device should not have any issues communicating if the timing parameters are under the specs from the datasheet.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

This is my write to the register after tweaking the pull-up resistors. They're actually a little low now...

This is the consequent read. Still reading twice and now it is 0x00. I think the 0x00 is because the Write above seems to be writing a 0x00 first, then 0x55 and finally 0x00... Unclear as to why that would be happening.

Bump.

Any comments on the above waveforms? My rise and fall times are .5uS, not fast enough for the Fast I2C, but within the requirement for the implemented 100kHz setup.