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SRC4184: A few concerns with the reset

David C
Expert 3350 points
Part Number: SRC4184
Other Parts Discussed in Thread: TPS3836

One concern I have regrading the SRC4184 is how to implement the reset.  The data sheet indicates that the reset must be done external to the device since it does not have an internal power-on-reset function.  Therefore, the clocks must be active before the RSTn in pulled low for 500ns, and then released.

My issue is that I am using this in a stand-alone configuration.  I don’t have a processor to generate a reset using a GPIO.  Are there any application notes that show how to implement a simple reset circuit for this device based on the absence or presence of the RCKIA/RCKIB inputs?

Regards,

David

  • 0
    TI__Expert 5645 points
    Hi David,
    SRC4184 can function is HW mode which typically do not have host processor controlling/configuring the I/Os of the SRC device. But we do not have any specific app notes outlining the implementation of reset circuit for this device based on ref clock presence.

    I'll have to look into some possible solutions but will have to test to validate it works reliably before sharing/publishing the same. Thanks.

    Best regards,
    Ravi
  • 0 in reply to Ravi Patil
    TI__Expert 3350 points
    We will be using this part in HW mode, and we do not have a processor available to issue a reset using a GPIO (for example).

    I was thinking through a possibility of using a reset supervisor (TPS3836) that could detect the 12MHz reference clock presence through an RC circuit with a diode, but that doesn’t have the capability of bringing the RESET output low after the clock starts to generate the actual reset of the SRC.

    Another option I thought of is to use a 4-bit counter (74LV161A), and use the 4th output as a “divide by 16” of the 12MHz clock. That will provide a divided clock period of 1.33us, which will have a low time of 667ns, enough for the SRC reset time. I just don’t have a solution for halting the counter. The inverse of the RCO output could be tied to one of the enable inputs to halt the counter when the count reaches 0b1111, but in order for the MSB to experience a HIGH-LOW-HIGH transition while the clock is running, the counter will reach 0b1111 twice.

    Anyway, I have spent a few hours trying to come up with a solution. That’s why I reached out to you to see if someone may have already solved this issue since the device doesn’t have an internal POR circuit.