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Original question:

Sampling rate of TLV320AIC3204.

TLV320AIC3254EVM-K: Steps for Configuring TLV320AIC3204 Sampling rate to >48kHZ

Juliana Cherston
Prodigy 145 points
Part Number: TLV320AIC3254EVM-K

Hello, 

I am using PurePath Studio to configure an AIC3204 eval module. I am able to use the graphical interface to adjust the sample rate up to 48kHz, but if I select rates >48kHz I start seeing junk output in all cases I can't find instructions anywhere in the user guide.

1) Can you please provide step-by-step instructions for how to configure the eval board to run at 96 kHz and at 192kHz?

2) Secondly, there is brief mention in the datasheet regarding the minidsp performance at 48kHz. Can the minidsp run at sample rates >48kHz, or is this a limit? 

For reference, my setup involves passing an impulse from a function generator into the input of the board, and displaying the output on an oscilloscope. 

Thanks! 

  • 0
    TI__Guru 57800 points

    Hi, Juliana,

    Welcome to E2E, Thanks for your interest in our products!.

    The EVM by itself is unable to provide the clocks required for operation above 48KHz sampling rate. This is a limitation of the USB-audio interface circuit used. In order to evaluate the device with higher sampling rates, you need to provide an external digital audio source to the EVM. For this, you can connect the external audio clocks to header J14 of the USB-MODEVM motherboard, but please consider that for this, you need to set the switches D4 and D5 of SW2 DIP switch to the OFF position. This will isolate the external clocks from the USB audio.

    The miniDSP is capable of operating with sampling rates up to 192 KHz. Please consider that for this, you need to use external audio source as described before. The availability of the sampling rates of the miniDSP is dependent of the Framework used in PurePath Console. Please refer to the frameworks help file for detailed information about the required framework for each sampling rate.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 145 points
    Hi Diego, thank you for the reply.

    To clarify based on your reply -

    1) Does this mean that the >48kHz sample rate is available only to I2S digital signals, then? Or is there any way to feed in an analog signal from a function generator?

    2) If limited to I2S, is this a constraint of the eval module or of the chip itself?

    3) I assume I should use I2S_In and I2S_Out blocks in PurePath studio, based on your answer to (1)

    4) Once I feed in mck, bck, and lrck as well as my input signal to J14, then should I expect my output signal to present at J14's output or at J6 Line Out?

    Thanks also for your note about selecting the appropriate framework.
  • 0 in reply to Juliana Cherston
    TI__Guru 57800 points

    Hi, Juliana,

    Please refer to below comments:

    1-The sampling rate depends of the I²S clocks and digital interface, internally the analog signals are sampled based on the configured sampling rate. Even if only the analog inputs/outputs of the device are used, the I²S clocks should be provided.

    2-The sampling rate limitation is not on the device itself, it comes from the USB-Audio interface IC, hence is an EVM limitation.

    3-It depends if the I²S inputs and outputs are used in your system.

    4-It would depend on the device  configuration and processing block created. The digital output of the device will be streamed on J14 of the motherboard, while the analog output can be configured to stream the audio signal over J6.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 145 points
    For 192khz single-channel processing, which clock values are strictly required and what clock rates are suitable?
  • 0 in reply to Juliana Cherston
    TI__Guru 57800 points

    Hi, Juliana,

    Speaking of the I²S clocks, for 192KHz, WCLK should have the same sampling rate frequency, BCLK depends on the data size being typically 32×Fs. The clock configuration of the device actually depends on different factors, including the selection of the clock that will be used as the source for the internal system clock, as well as the processing requirements of the miniDSP/Processing blocks.In general, the clocks are configured in PPS automatically when selecting the desired sampling rate. For example, a typical configuration for 192KHz sampling rate would be:

    • PLL ON:NADC/NDAC = 2
      • P = 1, R = 1, J = 8, D = 0
    • MADC/MDAC = 8
    • AOSR/DOSR = 32
    • WCLK = 192KHz
    • BCLK = 6.144 MHz.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 145 points
    Diego,
    Thanks for your continued help. I'm still trying to understand what signals exactly I am expected to feed into J14 in order to clock at 192kHz.

    On J14 I see pins for MCLK, BCLK, and LRCLK but no WLCK. In the AIC3254 datasheet I see 50MHz as a recommended value for MCLK. So for the 192KHz setup am I meant to feed 50MHz into MCLK, 6.144 MHz into BCLK, and leave LRCLK unconnected (for a single channel operation)? Where do I feed in WCLK?

    Or by "the clocks are configured in PPS" do you mean that these clocks are generated internally?
  • 0 in reply to Juliana Cherston
    TI__Guru 57800 points

    Hi, Juliana,

    First of all, I'd like to clarify that WCLK is the same clock as LRCK, it's just that I was working this morning with a device which uses a different term for the word clock. Sorry for the confusion.

    The mention of 50MHz spec is for the maximum accepted value for the MCLK clock, not a recommended value. For a 192KHz application, I would recommend to use audio type clocks for the master clock, like either 12.288 MHz or 24.576 MHz . If these frequencies are not supported, 24MHz would be good. 50MHz is actually not supported by the PLL for the internal clock generation.

    For your application, please connect a 192KHz clock to LRCK pin.

    My mention is about PPS configuring the clocks for the general device evaluation from a known MCLK, like 12.288 MHz. The clock settings can be found in the system settings code, please refer to this wiki link for more information about this. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 145 points
    Diego, you've been so helpful! Thank you.