CCS/TLV320AIC3206: power/ voltage hum when connected phone or laptop output to the codec line in input

Hi, V Pot,

The issue with the hum you are hearing may be related to the power supply not being clean or an internal issue where the common mode voltage of the device is not being regulated properly. Have you analyzed the output signal to identify the frequency and amplitude of the humming noise?. Also, it would be helpful if you can look in the power rails for a similar noise.

Regarding your second question, in general it will depend on the application, but for your particular case, as you have digital filters to remove noise after the ADC, as you mention it would be better to use the ADC volume control.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

diego,

these are the common mode settings for input im using

AIC3206_write( 54, 0x03 );  // CM_1 (common mode) to LADC_M through 40 kohm
AIC3206_write( 57, 0x03 );  // CM_1 (common mode) to RADC_M through 40 kohm

following is the hum and it increases when i touch the phone it is connected to

Diego,

Can you please take a look at my reply above and provide me the solution for the problem. If not please forward it to the right person, we are just stuck without making progress on this issue.

V Pot,

I have been busy last couple of days and haven't had a chance to get back to you. The noise you are showing seems high, but I cannot see the amplitude of your plot, can you share it?. This is not an expected behavior of the device so it makes me think the problem is with either the input source or the boost pack used. Can you compare the  noise spectrum of the input signal before the ADC and after?. I don't have the same board but with the EVM I am unable to see the noise. Can you also check if the noise is also affecting the analog power rails?

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Hi Diego,

Sorry for cropped pic. The noise is around -34db.

1) how to check if noise affecting analog power rails? My booster pack is powered from laptop usb.

2)did you check if the hex values for common mode registers I’m using are right?

continuation to above reply...

3) since aic3206 on boosterpack runs on 1.8v power supply. giving analog aux input from laptop or mobile phone can damage the adc right?

Hi, V Pot,

Thanks for the additional info.

1- Please monitor REF pin as it is the internal reference decoupling point and look for any noise.

2- The common mode settings you are configuring are fine, there is no difference in using CM1x or CM2x. 

3-  it may happen if you apply a signal which amplitude is above the absolute maximum ratings. Did you noticed a different behavior before and after applying your input signal?. Is is possible to check in a different booster pack if the same settings produce same noise?. Actually, can you please check if the noise is there without applying any input signal?. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Diego,

1)I ordered another booster pack. Will update you on that

2) I don’t here the hum when I don’t connect any input source... but even if i touch the aux with my finger it hums.

3) i ran a preamp circuit with 9v single supply and connected its output as input to boosterpack once before . It would be possible that the input would be out of its range. But it should clip but not make hum right?

Diego,

1) I tried with a new boosterpack and same settings, i hear same hum.

2) i correct myself, the hum is there even if i don't connect an input source, but it would be less compared to hum when connected input audio source.

3) i'm pretty sure its something wrong with the settings. please look carefully into my settings below and try to resolve this issue. thanks, if not possible forward it to boosterpack experts who can resolve it. I need this problem fixed asap

 /* Configure AIC3206 */
	    AIC3206_write( 0,  0x00 );  // Select page 0
	    AIC3206_write( 1,  0x01 );  // Reset codec
	    C55x_delay_msec(1);  		// Wait 1ms after reset
	    AIC3206_write( 0,  0x01 );  // Select page 1
	    AIC3206_write( 1,  0x0a );  // Disable crude AVDD generation from DVDD
	    AIC3206_write( 2,  0x01 );  // Enable Analog Blocks, use LDO power
	    AIC3206_write( 123,0x05 );  // Force reference to power up in 40ms
	    AIC3206_write( 124,0x06 );

	    C55x_delay_msec(40); 		// Wait at least 40ms
	    AIC3206_write( 0,  0x00 );  // Select page 0

	    /* PLL and Clocks config and Power Up  */
	    AIC3206_write( 27, 0x0d );  // BCLK and WCLK are set as o/p; AIC3206(Master)
	    AIC3206_write( 28, 0x00 );  // Data ofset = 0
	    AIC3206_write( 4,  0x03 );  // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
	    AIC3206_write( 6,  0x07 );  // PLL setting: J=7
	    AIC3206_write( 7,  0x06 );  // PLL setting: HI_BYTE(D=1680)
	    AIC3206_write( 8,  0x90 );  // PLL setting: LO_BYTE(D=1680)
	    AIC3206_write( 30, 0x88 );  // For 32 bit clocks per frame in Master mode ONLY
	                               	// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
	    AIC3206_write( 5,  0x91 );  // PLL setting: Power up PLL, P=1 and R=1
		C55x_delay_msec(1); 		// Wait for PLL to come up
		AIC3206_write( 13, 0x00 );  // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
		AIC3206_write( 14, 0x80 );  // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
		AIC3206_write( 20, 0x80 );  // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
		AIC3206_write( 11, 0x87 ); // Power up NDAC and set NDAC value to 7
		AIC3206_write( 12, 0x8C ); // Power up MDAC and set MDAC value to 12
		AIC3206_write( 18, 0x87 ); // Power up NADC and set NADC value to 7
		AIC3206_write( 19, 0x8C ); // Power up MADC and set MADC value to 12


	    /* DAC ROUTING and Power Up */
	    AIC3206_write( 0,  0x01 );  // Select page 1
	    AIC3206_write( 12, 0x08 );  // LDAC AFIR routed to HPL
	    AIC3206_write( 13, 0x08 );  // RDAC AFIR routed to HPR
	    AIC3206_write( 0,  0x00 );  // Select page 0
	    AIC3206_write( 64, 0x02 );  // Left vol=right vol
	    AIC3206_write( 65, 0x00 );  // Left DAC gain to 0dB VOL; Right tracks Left
	    AIC3206_write( 63, 0xd4 );  // Power up left,right data paths and set channel
	    AIC3206_write( 0,  0x01 );  // Select page 1
	    AIC3206_write( 16, 0x03 );  // Unmute HPL , 0dB gain
	    AIC3206_write( 17, 0x03 );  // Unmute HPR , 0dB gain
	    AIC3206_write( 9 , 0x30 );  // Power up HPL,HPR
	    C55x_delay_msec(1 );        // Wait 1 msec

	    /* ADC ROUTING and Power Up */
	    	    	    AIC3206_write( 0,  0x01 );  // Select page 1
	    	    	    AIC3206_write( 52, 0x40 );  // STEREO 1 Jack
	    	    	                               	// IN2_L to LADC_P through 40 kohm
	    	    	    AIC3206_write( 55, 0x40 );  // IN2_R to RADC_P through 40 kohmm
	    	    	    AIC3206_write( 54, 0x03 );  // CM_1 (common mode) to LADC_M through 40 kohm
	    	    	    AIC3206_write( 57, 0x03 );  // CM_1 (common mode) to RADC_M through 40 kohm
	    	    	    AIC3206_write( 59, 0x50 );  // MIC_PGA_L unmute
	    	    	    AIC3206_write( 60, 0x50 );  // MIC_PGA_R unmute
	    	    	    AIC3206_write( 61, 0x20 );
	    	    		AIC3206_write( 51, 0x00 );      // SetMICBIAS

	    	    	    AIC3206_write( 0,  0x00 );  // Select page 0
	    	    	    AIC3206_write( 81, 0xc0 );  // Powerup Left and Right ADC
	    	    	    AIC3206_write( 82, 0x00 );  // Unmute Left and Right ADc
	    	    	    AIC3206_write( 83, 0x00 );  // Unmute Left and Right ADC
	    				AIC3206_write( 84, 0x00 );  // Unmute Left and Right ADC
	    				//AIC3206_write( 86, 0x80 );  // L-AGC configuration
	    				//AIC3206_write( 94, 0x80 );  // R-AGC configuration

	    C55x_delay_msec(1 );        // Wait 1 msec

please don't follow the comments in the code, they won't make sense. just look at the register number and its value.

V Pot,

Thanks for the feedback, it is important to understand if the noise is present without input signal. I have been swamped lately but will try to check the register settings in detail and see if the issue is coming from here.I may be able to get back to you by the end of the day. Just to verify, is the codec configured as Master?, if yes, is 12.288MHz the clock used? (based on the comments). Have you done any modification to the booster pack? I would like to know if the schematic and connections are the same than the one available in ti.com (http://www.ti.com/lit/df/sprr233/sprr233.pdf.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Diego,

1)Yes the codec is master
2) what do you mean by same schematics? I’m using c5545boosterpack from ti so obviously it would be same.

3) so the hum comes in when connect an aux and it increases when I connect the other end of aux to audio source

V Pot,

Thanks for the feedback. I ask because many customers modify the boards for specific end-system reasons. I have a couple comments.

Based on the information from your code, 12MHz is the MCLK frequency and sampling rate is 8KHz. The BCLK dividers from your settings is generating a clock of 1.536MHz, which is not meeting the rest of the configurations for a sampling rate of 8KHz in I²S mode, but can work for a TDM bus. For correct I²S operation with 16-bit data and 8KHz sampling rate, BCLK divider should be 48.

The gain configured is 40dB on the input PGA, which is actually quite high for a line input, if there is a small noise, it will be increased drastically; I recommend to reduce the gain to 0dB and adjust it accordingly.

The common mode selected should be the same for the input and CMx connection to the PGA. One is connected to 10K and the other to 40K, before you only shared the CM settings, but these should match the input impedance of the input signal.

Page 1 Register 0x3D is not set correctly, it cannot be configured as 0x20. Please use 0x00 instead.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Diego,

Thanks for taking time and debugging.

Can you list out the register number and values to be set in a detailed way for bclk and other things you mentioned so that I don’t do anything wrong this time.

Like ‘register number’ : ‘value’

Because those values were given by you in a different thread. So i set those like that.

Are rest of the settings look fine?

Diego,

I changed the bclk divider N value to 48 and booster pack still don’t transmit i2s signal. I tried scoping it and no signal. From i2s1 pins on j7 header of booster pack.

Do i need to change any other settings like i2c ? Please advise. Thanks

V Pot,

The register settings I provided before have some differences with the code you shared; some of the incorrect settings I identified are correct in the code sent. Please refer to below:

BCLK Divider to 48:
Page 0, Register 30: 0xb0

Input PGA Gain set to 0dB:
Page 1, Register 59: 0x00
Page 1, Register 59: 0x00

Set input impedance to 10K for all the used inputs:
Page 1, Register 52: 0x40
Page 1, Register 54: 0x40
Page 1, Register 55: 0x40
Page 1, Register 57: 0x40

ADC Power Tune:
Page 1, Register 61: 0x00

The rest of the registers seems fine.

Regarding your last message, the I²S signals should be coming out fro the codec as it is being configured in Master mode. I have seen a similar behavior as a result of an incorrect setting on the BCLK Divider register when configuring the codec as master, please make sure the divider is turned ON. With above setting of register 30 you should not have issues. 

From the codec point of view, there is no other required configuration, so maybe the problem is related to the booster pack processor. 

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Diego,

Yes I’ve used exact same settings over the weekend and was still not able to get any i2s output though

V Pot,

This seems really strange, the register configuration works correctly in my EVM as Master mode. I would recommend you to verify that the MCLK provided to the device is correct and check as well if the processor is writing correctly the settings into the device.

I am afraid I cannot give much help if there is a system-level issue which somehow could be affecting the codec. Codec-wise, there is no issue with the register settings.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

diego,

can you test it using a c5545 booster pack? instead the evm? that way you'll know better

VPot,

I don't have a booster pack right now, I need to order one, so It may take some days for me to get it and make the test.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Diego,

I can fast ship one to you if you want

V Pot,

I have ordered one. Please expect some feedback by the end of the week. Please note that I can help to identify issues with the codec itself on that particular board, but I have no experience with that platform and cannot offer a lot of help on the programming or processing side. If there is a problem or you need help with the processor, I will not be able to help, so you should contact my colleagues on the C55xx forum.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Diego,
Thanks for the help.

But i doubt if the issue is with codec, I’m assuming its mostly with boosterpack settings for i2c . Lets see

Diego,

mean while i made some progress and the i2s pins on the boosterpack transmitting ....but the audio is distorted clipped. i've attached the recordings. Output from the headphones is fine, no distortion issues. could that be some drift duw to clock mismatch or something. let me know what you think of it after listening to the audio clips. Thanks

I2s Recording.m4a

Recording I2s1.m4a

V Pot,

The audio you sent sounds really bad, have you checked the gain in the input PGA?. If there is no issue with the headphone output (assuming input is coming from the DAC), the problem can be tracked to the ADC, so I don't think there is a clock problem as DAC is working fine. Do you find the audio distorted even if applying a small input signal?

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Diego,

The input for headphone output and the i2s outputs are just one and the same. The input is from line in jack which goes through adc and this digitalized signal is written to both dac and i2s pins... from dac the headphone output sounds perfect no distortion but the i2s pin output is distorted as I recorded.

Pga gain is zero.

I don’t know may be the writing samples rate is messed up with i2s pins case. I assume

VPot,

Thanks for the feedback and clarification. This indicates the codec is working fine as audio playing on the headphone is fine. This suggests a problem with the way the processor is reading the I²S data.  

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer