Tool/software: Linux
Hi,
I am trying to setup the TLV320ADC3101 as a master on an i2s bus. I am supplying an MCLK on pin 24 at 4.0 MHz and have been able to get BCLK and WCLK at the correct frequencies out of the chip without issue so long as I write a 1 to D2 of Page 0 / Register 29. However, I receive no DOUT signal. To me, this means that my 'codec is powered down' - but I am not sure what to try next. I am using the PRB_R1 processing block and would have expected that DOUT on pin 3 should have started shipping data. When viewing the signal line on an Oscilloscope all I get is a held high signal.
I have reproduced my register writes below. My ADC chip is at address 0x18, and the register and data bytes are in hex. Am I missing something simple? Is the order of my register writes incorrect? Any guidance would be greatly appreciated.
# Set Register Page to 0
i2cset -y -f 2 0x18 0x00 0x00
# Software Reset to Control register defaults
i2cset -y -f 2 0x18 0x01 0x01
# Configure Clock-Gen Multiplexing for PLL_CLKIN (MCLK) and CODEC_CLKIN (MCLK)
i2cset -y -f 2 0x18 0x04 0x00
# Create the K value for the PLL clock generator (K = J.D)
# Program the P (1) and R (1) values of the PLL
i2cset -y -f 2 0x18 0x05 0x11
# Program the J value of the PLL (22 in this case)
i2cset -y -f 2 0x18 0x06 0x16
# Program the D MSB value of the PLL (57 in this case)
i2cset -y -f 2 0x18 0x07 0x39
# Program the D LSB value of the PLL (92 in this case)
i2cset -y -f 2 0x18 0x08 0x5C
# Power the PLL on (and retain P and R settings)
i2cset -y -f 2 0x18 0x05 0x91
# Allow PLL time to come online.
sleep 1
# Program the NADC (8) and power it up
i2cset -y -f 2 0x18 0x12 0x88
# Program the MADC (2) and power it up
i2cset -y -f 2 0x18 0x13 0x82
# Program the ASOR (128)
i2cset -y -f 2 0x18 0x14 0x80
# Program the ADC Audio Interface Control #1
# i2s / 16 bits / BCLK output / WCLK output / 3-stating of DOUT enabled
i2cset -y -f 2 0x18 0x1b 0x0D
# ADC Interface Control #2 BCLK and WCLK active
i2cset -y -f 2 0x18 0x1d 0x06
# BCLK N Divider (16) and powered on
i2cset -y -f 2 0x18 0x1e 0x90
# i2s TDM Control Register
# Channel Swap Disabled / Both Left and Channel Enabled
# early_3-state enabled / time_slot_mode_enabled
#i2cset -y -f 2 0x18 0x26 0x07
# Program the processing block to be used (PRB_R1)
i2cset -y -f 2 0x18 0x3d 0x01
# DOUT Control (DOUT bus keeper disabled / primary DOUT output for codec interface)
#i2cset -y -f 2 0x18 0x35 0x02
# Change Register Page 1
i2cset -y -f 2 0x18 0x00 0x01
# MICBIAS - 2V BOTH
i2cset -y -f 2 0x18 0x33 0x28
# Right Analog PGA = 40dB Gain
i2cset -y -f 2 0x18 0x3C 0x50
# Left Analog PGA = 40dB Gain
i2cset -y -f 2 0x18 0x3b 0x50
# Left ADC Input selection for Left PGA = IN1L(P) as Single-Ended
i2cset -y -f 2 0x18 0x34 0xfc
# Right ADC Input selection for Right PGA = IN1R(M) as Single-Ended
i2cset -y -f 2 0x18 0x37 0xfc
#Set Register Page to 0
i2cset -y -f 2 0x18 0x52 0x00
# ADC Digital - Left and Right ADC powered up
i2cset -y -f 2 0x18 0x51 0xc2
# Unmute both ADC's
i2cset -y -f 2 0x18 0x52 0x00
