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DIX4192: Regarding lock condition of PLL

Noriaki Fukazawa
Expert 1620 points
Part Number: DIX4192


Hi Expert,

My customers are considering DIX4192.

I would like advice on the following questions of my customers.

<Question>
Is the frame structure of AES 3 involved in the LOCK condition of the PLL?
For example, if the frame can not be recognized, the clock regeneration of the bit stream
Even if it is possible, it will not be LOCK.

Best,Regars.

Noriaki

  • 0
    TI__Guru 57800 points

    Hi, Fukazawa-san,

    I have notified my colleague about your question, he will get back to you as soon as possible.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Expert 1620 points
    Hello Diego-san,

    Thank you for your reply.
    I am waiting for your reply.

    Best Regars.
    Noriaki
  • 0 in reply to Noriaki Fukazawa
    TI__Expert 5645 points
    Dear Fukazawa-san,
    LOCK output is active only when both the AES3 decoder and PLL2 indicate a lock condition...

    Just as additional info regarding the block, DIR has PLL1 and PLL2 blocks along w. AES3 decoder. The DIR requires a reference clock, supplied by an external source applied at either the RXCKI or MCLK. PLL1 multiplies the reference clock to a higher rate, which is used as the oversampling clock for the AES3 decoder. The decoder samples the AES3-encoded input stream in order to extract all of the audio and status data. The decoded data stream is sent on to a de-multiplexer, where audio and status data are separated for further processing and buffering. The pulse generator circuitry samples the encoded input data stream and generates a clock that is 16 times the frame/sampling rate (or fS). The 16 fS clock is then processed by PLL2. For the LOCK bit to be active, both AES3 decoder [which implies AES3 frame] and PLL2 block have to involved.

    Best regards,
    Ravi