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ADC34J45EVM: JESD clocks have not output

user1154396
Prodigy 210 points
Part Number: ADC34J45EVM
Other Parts Discussed in Thread: LMK04828

I am using ADC34j45EVM with FPGA.  I follow the steps in the user guide:

1. The evaluation of the ADC32J/34Jxx EVM requires programming the LMK04828 clock source with the
correct PLL settings to provide a 160 Msps clock.
• Connect a USB cable from the ADC32J/34Jxx EVM to the PC
• Open the ADC3000 GUI, and connect to the ADC32Jxx or ADC34Jxx EVM
• Go to the Low Level tab and click Load Config
• Browse and find the ADC3xJxx_160MSPS_Operation_LMK_Setting.cfg
• Check that the PLL2 LED D4 is lit – this indicates that the PLL is programmed properly and the
correct clocks are being generated

After I loaded the  "ADC3xJxx_160MSPS_Operation_LMK_Setting.cfg" .  The PLL2 LED D4 is lit.

However, I found the clocks GTX_CLKP/M and CLK_AL0_0P/M in circuit schematic have no output. Why? Is there any setting?

  • 0
    TI__Mastermind 44480 points
    We have received your question. One of our ADC experts will provide a more detailed response soon.
    Best regards,
    Jim B
  • 0
    TI__Genius 12780 points

    Hi User1154396,

    Do you have the ADC34J45EVM connected to a capture card (like the TSW14J56EVM )?

    The CLK_LA0 signals are not enabled by default. Open the ADC3000GUI and load the configuration file "ADC3xJxx_160MSPS_Operation_LMK_Setting.cfg". Click on the LMK04828 tab, you can uncheck the "Group Powerdown" box for "CLKout 8 and 9". Configure as seen in the picture below.

    If you probe R22, you should see a 320 MHz signal. Additionally, you should see the GTX_CLK when probing R92 with no additional configuration changes. See that "CLKout 2 and 3" are not powered down.

    Best Regards,

    Dan