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ADC12DL3200: LVDS Synchronization

Gianpiero Panci
Prodigy 40 points
Part Number: ADC12DL3200

Hi, I would need a specific information on the Synchronization behaviour of the component. The question is simple and direct, I am developing the FPGA firmware to manage the ADC LVDS data signals,

does the activation of  SYSREF signal reset the DACLK/DBCLK.. signals? or reset only the demultiplexing of the data?

  • 0
    TI__Mastermind 43910 points
    Hi Gianpiero
    The applied SYSREF signal sets or re-aligns the timing of the de-multiplexed output Dx data signals, DxSTRB strobe signals and the DACLK/DBCLK/DCCLK/DDCLK/ output clocks.
    If a new SYSREF event is performed which does not change the existing timing (because SYSREF is frequency and phase locked to CLK and is at the proper frequency and setup/hold time), those signals would not be affected.
    Let me know if you need any additional information.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 40 points
    Hi Jim,

    thank you for the ready answer, just to be sure that I have understood well, at the first activation of the SYSREF signal I should expect a re-aligning of the DACLK/DBCLK/DCCLK/DDCLK/ output clocks (that means a discontinuity of them, shorter/longer cycles) and after, if the SYSREF frequency and phase lock is correct the DACLK/DBCLK/DCCLK/DDCLK/ output clocks should not more impacted by the SYSREF activation. Correct?
  • 0 in reply to Gianpiero Panci
    TI__Mastermind 43910 points
    Hi Gianpiero
    That is correct.
    Best regards,
    Jim B