TSW1400EVM firmware source

Hi, Jim,

It's a great help.
This is the first time I program FPGA firmware.
I will do my best.

Best regards,

Hello,

I have a problem to make costom firmware for TSW1400 with ADS5263EVM.

When I use costom firmware, HSDC Pro shows "Frame clock error in Read DDR to file".
If I change "check_fclk=0" in .ini file, this message does not shown.

I almost do not change source from Jim.

I want to know:
(1) How HSDC Pro knows frame clock is OK or NG ?
(2) Where does the firmware check "frame clock mapping Index" ?

Regards,

Takahashi,

What are you attempting to change? What changes did you make? If the frame clock is OK, HSDC Pro will do a valid capture. If there is a problem with the frame clock, you will get the message you are receiving. There are currently six ini options available in HSDC Pro. What is your reason for attempting to create a seventh version? Please send your ini file if you made other changes than the one mentioned in your post and we will take a look at it.

Regards,

Jim 

Hi, Jim,

------
<Final Goal>
I want to make costom firmware.

<First Step>
I want to know the firmware source for ADC_FIRMWARE.rbf.
After I know this, I want to try changing the firmware for my goal.
-----

I thought the firmware source from Jim is source for ADC_FIRMWARE.rbf.
But, .rbf made from this source does not process correctly. "Frame clock error in Read DDR to file" is shown.

Next, I changed the firmware source to remove this error. But, this is not yet succeeded. So, I made previous post.
I changed defines.vh, adcif.v, and adcif_formatpdata.v for this.

I had used ADS5263_2W_16b_bytewise.ini.

Please tell me that I need to change to remove frame clock error.

Best regards,

Takahashi,

Here is some more info that I hope helps you with your issue:

Regards,

Jim

 Make sure the mode (Bytewise/Wordwise, 14b/16b/18b) set in the device GUI matches with the INI file selected in HSDC pro. Some information about Frame clock implementation of firmware is below. Frame clock signal is used to detect the start of a valid sample. Rising edge of Frame clock is considered as the start of a sample. check_fclk has to be set to 1 in INI file if the device has Frame clock.

When Capture button is pressed in HSDC Pro, frame_clk_en signal (Config_7[3:3] register in dumpmem_config module) would be set to high from HSDC Pro. Firmware would then keep sending the data of frame clock, sampled with clk_adc. Please refer pack_data module to know the format of frame clock data (din0_frm, buffer_frm) that is sent to HSDC Pro. HSDC pro would try to match the Frame clock data with Frame clock codes defined for the selected mode of the device (These codes are generated in HSDC pro based on the output format of ADC). If the codes does not match, HSDC pro will keep adjusting the bitslip of deserializers (Through config[4], config[5] registers in dumpmem_config module ) till the frame clock codes are matched. Once the frame clock codes are matched, frame_clk_en would be reset and then firmware would send actual ADC codes. If Frame clock codes are not matched even after bitslip adjustments HSDC pro throws the error "Frame clock error in Read DDR to file". Frame clock mapping Index and Channel Mapping Indexes of INI file are sent to firmware through configuration registers (frame_clk and Channel1-Channel32 in dumpmem_config module). These are used in channel_select_n_reorder module to reorder the data from deserializers based on what pins of Samtec connecter are connected to selected device.   See the attachement for more info. Firmware_DLL_Design_Document0.3.docx

Hi, Jim,

Your information and document were helpful for me.
I was able to understand this firmware more deeply. Thanks.
However, I cannot get a good result yet.

This document(information) contains modules:
channel_select_n_reorder
invert_4bits
pack_data

But, the firmware from Jim does not contain these modules.
Could you give me firmware that contains these modules?

Also, I hava a question about INTERFACE_ID.
INTERFACE_ID is shown as "Interface Type" in HSDC Pro.
When I only changed INTERFACE_ID, results of Capture is also changed.
"TIMED_OUT_ERROR" was shown.
Does HSDC Pro change the control to firmware according to INTERFACE_ID?

Best regards,

Takahashi,

Here is more info from our contractor regarding your issue:

 He is using ADS5263, 2W_16b mode. The firmware you had sent seems to be ADC_SAMPLE_WISE.

We have a format specific firmware which supports 2W_12b, 2W_14b and 2W_16B for ADS5294. we could possibly share this firmware (//HPA/MHR/Projects/TSW1400/TSW1400_ADC_FPGA_code/FPGA Firmware/V1.11/Firmware Archive/TSW1400_ADC_ver1.11.qar) and guide him on what changes he has to make for 2W_16b of ADS5293. The changes would be in defines.vh, adcif.v.

Following are the changes needed
1. In defines.vh,
  a. Comment "`define BITWISE_DDR_1W_12B" and uncomment "`define BITWISE_DDR_1W_14B". Implementation for BITWISE_DDR_1W_14B and BITWISE_DDR_1W_16B are same in adcif_formatdata.
  b. Assign ADC_BM0 to ADS5263_BM0 and define  ADS5263_BM0.
  c. Define INTERFACE_ID as 33
 
2. In adcif.v,
 Add a case for ADS5263_BM0 and assign pin numbers correctly for ADS5263 in order.
 
3. In TSW1400_IID_Lookup.csv present under HSDC Pro/1400 Details
   Add a new row for Interface ID, 33 - ADS5263_2W_16B
 
Use the atttached updtaed INI which also has support for format specific firmware. DLL_version parameter is removed in INI sothat parameters under [ADC] section would be active.  

Regards,

Jimhttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/73/ADS5263_5F00_2W_5F00_16b_5F00_bytewise.iniTSW1400_ADC_ver1.11.zip

 

Hi, Jim,

Thank you for the detailed explanation.
However, I couldn't get a good result with this.

By the way, I'm worried about the result of Compilation.

(1) "TimeQuest Timing Analyzer" is red.
Slow 900mV 85C Model, Slow 900mV 0C Model, Multicorner Timing Analysis Summary, and Unconstrained Paths are red.

(2) Warnings more than 600.

(3) Quartus II Version.
I use Quartus II 64-Bit Version 13.1.0.

Particularly, I'm concerned about (1). Do I need to change some files or settings about timing?
Please give me advice of these.

Best regards,

Takahasgi,

Those Time quest analyser warnings can be ignored. Firmware would still work with those.

"I couldn't get a good result with this." from the post; Does the  mean you are still getting Frame clock error?  

Regards,

Jim

Hi, Jim,

Yes, I am still getting Frame clock error.

I changed files as you said.
But, some are different.

(1) In defines.vh,
Uncomment "`define BITWISE_DDR_2W_14B" instead of "`define BITWISE_DDR_1W_14B".
I think uncomment "`define BITWISE_DDR_1W_14B" you said is a mistake.

(2) In adcif_formatpdata.v,
Comment some lines in ADC - Bus 2 - 2W mode.
Because, these generated some error in Compilation. For example,
"15118 datain port of HSDI receiver atom ""rx_4" must be fed by input pin that does not feed any other logic".

Does Quartus II Version not affect?

Best regards,

Hi, Jim,

In addition to my previous post, I have a question.

Do I need to change the Settings?
(Quartus II Toolbar->Assignments->Settings...)

For example, when I changed "Perform Physical Synthesis for Combinational Logic for Performance = ON"(Compilation Process Settings->Physical Synthesis Optimizations), Capture data is changed.
Therefore, I think there is a optimum settings for correct performance.
Note: In this time, I changed "check_fclk= 0" in ini file to get the Capture data.

Best regards,

Hi, Jim,

I am using Quartus II with evaluation license.
This license has expiry date.
So, I do not have enough time for my evaluation test.

If I can make the firmware that process correctly, I will buy Quartus II license.

Please give me any advice.

Best regards,

Takahashi,

Are you still having issues with your design? Most of our firmware is done by a contractor. This is one reason why I cannot always help out customers with their issues. If you still have an issue, I can pass it on but it may take awhile before we get a response back. Try contacting an Altera rep and see if they can extend your trial period. They also have a very good support center that may be able to help with any issue's you stil may have.

Regards,

Jim

Hi, Jim,

Thank you for the rapid response.

I understood the reason. And, I will try to contact Altera about the license.
So, I can wait your response.

It would really be helpful, if you would answer to my post of Apr 22 and 23.

Best regards,

Can you share it again, please. I need that FW too. Thanks in advance.