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KCU105 support via TSW14J10EVM

Terraxion
Prodigy 140 points
Other Parts Discussed in Thread: ADC12J4000EVM, DAC38J84, ADC12J4000

I notice that the TSW14J10EVM Xilinx Firmware Source (Rev. C) contains source code and build scripts for various Xilinx boards VC707, KC705, and ZC706. 

Does the source code also support Xilinx KCU105 evaluation module?

I am trying to use the TSW14J10EVM to connect the ADC12J4000EVM to KCU105. 

  • 0
    TI__Genius 12965 points

    Ranjeet,

    We are working on that right now.  We will have some results in a couple of weeks.  One of the first devices we will verify will be the ADC12J4000 and DAC38J84.

    Ken.

  • 0 in reply to Ken C
    Prodigy 140 points
    Ken - sounds good, and thanks for the quick reply.
  • 0 in reply to Ken C
    Prodigy 140 points

    While waiting for the KCU105 support, I built the reference design targeted for KC705 and I had a question about the number of JESD lanes connecting the Virtex 7 FPGA on KC705 to the ADC on ADC12J4000EVM board. 

    I noticed that the JESD_PHY block is using 4 GTX transceivers each from Bank 117 and 118 for a total of 8 JESD lanes [1]. But according to the KC705 schematic, the FMC HPC connector is only wired to 4 GTX transceivers from Bank 118. The other 4 transceivers on Bank 117 are wired to SFP and SMA [2]. 

    How does the TSW14J10EVM reference design establish an 8-lane JESD connection to ADC12J400 on the ADC12J400EVM?

    [1] From the KC705 Reference design XDC:

    # Lanes [0-3] - Bank 118
    set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells -hier -filter {name =~ *top_level_block_jesd204_phy_0_gt_i/gt0_top_level_block_jesd204_phy_0_gt_i/gtxe2_i}]
    set_property LOC GTXE2_CHANNEL_X0Y13 [get_cells -hier -filter {name =~ *top_level_block_jesd204_phy_0_gt_i/gt1_top_level_block_jesd204_phy_0_gt_i/gtxe2_i}]
    set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells -hier -filter {name =~ *top_level_block_jesd204_phy_0_gt_i/gt2_top_level_block_jesd204_phy_0_gt_i/gtxe2_i}]
    set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells -hier -filter {name =~ *top_level_block_jesd204_phy_0_gt_i/gt3_top_level_block_jesd204_phy_0_gt_i/gtxe2_i}]

    # Lanes [4-7] - Bank 117
    set_property LOC GTXE2_CHANNEL_X0Y11 [get_cells -hier -filter {name =~ *top_level_block_jesd204_phy_0_gt_i/gt4_top_level_block_jesd204_phy_0_gt_i/gtxe2_i}]
    set_property LOC GTXE2_CHANNEL_X0Y10 [get_cells -hier -filter {name =~ *top_level_block_jesd204_phy_0_gt_i/gt5_top_level_block_jesd204_phy_0_gt_i/gtxe2_i}]
    set_property LOC GTXE2_CHANNEL_X0Y9 [get_cells -hier -filter {name =~ *top_level_block_jesd204_phy_0_gt_i/gt6_top_level_block_jesd204_phy_0_gt_i/gtxe2_i}]
    set_property LOC GTXE2_CHANNEL_X0Y8 [get_cells -hier -filter {name =~ *top_level_block_jesd204_phy_0_gt_i/gt7_top_level_block_jesd204_phy_0_gt_i/gtxe2_i}]

     

    [2] From the KC705 Schematic:

     

  • 0 in reply to Terraxion
    TI__Mastermind 44680 points

    Hi Ranjeet

    You are correct, the KC705 only has 4 RX lanes routed to the FMC connector. This limits the ADC12J4000 to the decimation modes that use 4 or fewer lanes when used with the KC705.

    The VC707 has 8 RX lanes, and does support the ADC12J4000 DDC Bypass mode which uses 8 lanes.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 140 points

    Jim, thanks for the confirmation on the number of lanes on KC705. 

     

    Is there a way to be notified when the KCU105 is added to the reference design and HSDC pro? 

  • 0 in reply to Terraxion
    TI__Guru* 91947 points

    Ranjeet,

    Not really. I would suggest sending another post asking about this in about 3-4 weeks.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 210 points

    Hello Jim, has this been released by now? I cannot seem to find it on the TSW14J10EVM page.

  • 0 in reply to Max M.
    TI__Guru* 91947 points

    Max,

    The firmware is released on the Xilinx website. We are still working on the User's Guide for this. We do have a preliminary copy I could send you. What TI EVM do you plan on testing with the KCU105?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 210 points
    By " on the Xilinx website" you mean the Link you sent me via private message? From my understanding the Hardware Demo is not firmware that works with the TSW14J10EVM and HSDC pro, or does it?
    I am basically looking for an updated version of slac690c since the TSW14J10EVM references support for KCU105.
    If you have a preliminatry copy of the guide, that would be great (and of the firmware if there is a seperate one). I will be testing the ADC12J4000EVM.
  • 0 in reply to Max M.
    TI__Guru* 91947 points

    Max,

    Yes. But I just realized that this firmware only supports a Xilinx provided GUI. We do have an internal firmware version that allows the user to connect TI EVM's directly to the KCU105 without the TSW14J10EVM and still be able to use HSDC Pro GUI through an Ethernet interface. This will be released in the very near future. The preliminary User's Guide is attached and I will send a link to the pre-released GUI in a private message.  

    Regards,

    Jim

    KCU105 User's Guide rough DRAFT.pdf 

  • 0 in reply to jim s
    Prodigy 210 points
    That is great, thank you! I checked the DRAFT and unfortunately the firmware still has the limitation of only sampling 32k samples (due to the memory limit of the internal FPGA memory). I plan to extend your firmware design to allow writing much more data to the 2GB DDR4 RAM. In case I accomplish this, would you be interested in the changes?
  • 0 in reply to Max M.
    Prodigy 210 points
    I will try to formulate an answer with the current state of things: two days ago, TI released revision 4.5 of the HSDC Pro Software (High Speed Data Converter Pro GUI Installer, v4.50 (Rev. Q) on www.ti.com/.../DATACONVERTERPRO-SW).
    It allows to connect via network to a KCU105 board once the included firmware is flashed to it as a .bit file in Vivado's Hardware Manager.
    The used firmware appears to be the Xilinx JESD Reference design firmware with the build target changed from XLOOP to TI. You can get it by applying for the JESD Lounge, the file name is JESD204B_UltraScale_Hardware_Demo_2016_1_v1.3.zip
    Just to be clear, I am not sure if changes were made to this firmware before shipping it with HSDC. It looks similar to me on the UART output. Clarification would be greatly appreciated.

    TSW14J10EVM is NOT required for this mode, since all communication is done via ethernet instead of the TSW14J10EVM's USB port. TI should add this fact to the TSW14J10EVM which currently still says that TSW14J10EVM supports the KCU105.

    On a side note I still have trouble actually getting it to work with ADC12J4000 but I will create a seperate thread for that issue.
  • 0 in reply to Max M.
    TI__Guru* 91947 points

    Max,

    The compiled version of firmware (svf file) on the Xilinx website should be included with the latest version of HSSDC Pro. You do not need the TSW14J10EVM with this setup. This will be noted in the next release of the TSW14J10EVM User's Guide. See if the attached updated KCU105 User's Guide helps you. We are still working on getting this document released and if you have any suggestions or comments regarding it, please let us know.

    Regards,

    Jim

     2526.3073.KCU105 User's Guide rough DRAFT.pdf

  • 0 in reply to jim s
    Prodigy 210 points
    Hello Jim,
    thank you for the draft, I think it is the same that I had already seen. I have created a seperate post for my problems with getting this working:
    e2e.ti.com/.../567648

    Any help would be appreciated.