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ADC32RF45: Clocking options to minimize power

Mark Guastaferro
Genius 11645 points
Part Number: ADC32RF45
Other Parts Discussed in Thread: LMX2582, LMK04828, LMK04610

Doing an architecture analysis for a proposed receiver with the ADC32RF45.  The ADC will be clocked at 3 GSPS, and Decimation mode will be set to divide-by-24 complex. Need to understand the lowest power clocking configuration. The assumption is a LMX2582 will be used to generate the CLKIN signal for the ADC.  What is the best low power option to generate SYSREF(s)?

The EVM uses the LMK04828 to generate SYSREF and the FPGA Clock/SYSREF. But this seems like a high power solution for generating SYSREF as the data sheet shows the LMK04828 consuming about 1.9W. This spec assumes all outputs are enabled, so maybe its lower in the described operating scenario where only a few outputs are needed. Or maybe there's an alternate method/device to generate SYSREF?

Speaking of power, how does selection of the decimation mode impact power?  Data sheet specifications show power dissipation at 6.5-7W, but in bypass mode. Also, does more decimation help the power consumption of the JESD SERDES block since the output rate rate is lower?  

  • 0
    TI__Mastermind 29220 points

    Hi,

    The LMK04828 not only supplies SYSREF to the ADC, but it also supplies device clock and SYSREF to the FPGA that completes the JESD204b link.   If you remove the LMK04828 you would still need to provide these three signals.   Since the LMX2582 has two clock outputs, you could use the second output to provide the device clock to the FPGA, but that leaves the SYSREF signals.   You only need to have the SYSREF signals to establish a link and then the SYSREF can be turned off.  But if the link is disrupted for any reason and must be restablished then you would need to turn on SYSREF again.

    I have seen applications where the SYSREF would be generated by an FPGA or other source, but for deterministic latency the SYSREF signal would need to be tightly controlled in timing with the device clock to the FPGA and with the sample clock to the ADC to meet setup/hold time.   The LMK makes the SYSREF generation easy and synchronous to the clocking, but at a cost.    The clocking forum would be best to ask how to minimize the power of the LMK04828 or if there is a lower power alternative to that device - such as the LMK04610 which i am told is lower power but i do not have quantitative data in hand for that.    It may be possible to use an LMK device to create SYSREF for link initialization and then power down the LMK once SYSREF is no longer needed, but that might make for a very long re-initialization time later on, and there may be other complications if the SYSREF to the FPGA were AC coupled for example.

    Power dissipation of the ADC32RF45 does depend a small amount on decimation mode, as shown in table 117 of the datasheet.  But in that table the only large effect on power comes from turning off one channel.  Higher decimation factors contribute a small amount of power savings but for the most part power dissipation is fairly flat across different modes of operation for a given sample rate. 

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    TI__Genius 11645 points

    Thanks, Richard,

    I'll post to the clocking forum for their suggestions on SYSREF.

    Thanks for pointing out Table 117, somehow we missed this when reviewing the data sheet..