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DAC3283EVM: Compatibility with Xilinx KC705 or Genesys 2 boards

Part Number: DAC3283EVM
Other Parts Discussed in Thread: FMC-DAC-ADAPTER, DAC3283, TIDA-00069, DAC3482, ADS4249

Hello,


I wonder if this EVM, together with the $50 adaptor are pin compatible with Xilinx KC 705 FPGA board connector (Right on or left one?)


www.xilinx.com/.../ek-k7-kc705-g.html

Or with Digilent Genesys 2 EVM?
store.digilentinc.com/.../


Is there any source code (VHDL/VERILOG etc.) for running this EVM?


Regards,

  • Hello Aronii,
    I see that the DAC3283 is compatible with the FMC-DAC-Adapter available from TI.com. For future reference a compatibility table is available from the literature document on the FMC-DAC-Adapter product page. It is missing some of the newest ADC/DACs, but the DAC3283 is included.

    For a firmware reference design I would point you to the TIDA-00069 document which describes Data Converter interface to Altera FPGAs. I think you will find the firmware reference design helpful when designing the Xilinx firmware.

    Regards,
    Brian
  • Brian,
    Thanks fo ryour quick response.
    It seems like you did not understand my question.
    I know that the DAC3283 is compatible with the FMC-DAC adapter. It is obvious since the adaptor is offered on the DAC3283 EVM web page and there is also a picture of both boards (EVM and the adaptor) connected together.
    My question was wether this adaptor (The other side - not the side which is connected to TI's EVM) is compatible with the 2 xilinx evaluation boards that I mentioned. Those boards - "KC705" and "Genesys 2" are not mentioned anywhere in the documentation, although the connector looks the same (Is it the same pinout? Same pitch?).
    Bedides that, the source code is a QAR binary file (Altera Quartus) - not exactly usefull for Xilinx chips...
    If you could find the VHDL/Verilog source codes of those files it would be very helpful.
  • Aronii,
    Ah, I see. The connection of concern on the FMC-DAC-Adapter is an industry standard FMC interface and will route signals correctly to a properly designed FPGA board with an FMC connector. We utilize the low pin count (LPC 160pin) pinout for maximum flexibility and compatibility with FPGA boards.

    The KC705 Kintex platform board has two FMC connectors 1 LPC and 1 HPC configuration. Either of these is suitable to connect with the FMC-DAC-Adapter.

    The Digilent Genesys 2 has a single FMC connector routed with HPC configuration. This is suitable for use with the FMC-DAC-Adapter.

    The other concern about interfacing would be the ability of the FPGA board to run at a high enough clock rate to interface with the DAC. The Kintex platforms you have listed are just fine from this angle.

    I understand it is not ideal to download the Quartus software the view the QAR project and HDL sources. I am trying to see if we have any LVDS firmware design for Xilinx available. I will need to get back with you early next week about this.

    Regards,
    Brian
  • Hello Aronii,

    I have checked and we do hot have a design we can release at this time on a modern Xilinx device.

    Regards,

    Brian

  • Hello,

    I understand that you don't have any source code to provide for Xilinx FPGA, but to be honest, I looked at the internet and I found some "unhappy customers" saying that TI's boards do not fit the new Xilinx boards (like KC705).

    I found a blog from someone who said that they bought some TI's boards and they had to cut the PCB's in order to fit them to the board and then the cunnector did not sit correctly and had a bad contact problems.
    It is written in Xilinx forums but they don't specify which TI boards did they use.

    I expect that if TI is selling adaptors for Xilinx boards, with FMC connectors, that someone will test that they work...
    If I will buy those boards and adaptors (one for DAC and one for ADC) would TI refund me for them if they don't fit or work?
    Those boards cost $299 + $499 + $49 + $49 = $896 which is not a negligible amount of money...
    So please help me in checking the mechanical issue as wel as pin compatibility.
    As for source codes: Can anyone send the Altera VHDL files of those boards? (VHDL not encrypted project files) I need for ADS4249 and for DAC3482 EVMs which are both offered with additional XIlinx adaptor.
    I know that the VHDL files it would not compile in Xilinx software but at least something to start with. You don't expect me to get a license from Altera and install their software just to get a look into those files.
    This is the minimum help that you can provide.
  • Hello Aronii,
    Wanted to give you an update on this.

    I have ordered internally both the adapter boards we are discussing. I will check them with the KC705 board I have on hand and let you know what I figure out.

    I have also checked your license issue and understand that you would need a paid-for version of Quartus to open the project. I am working with my team to see if/how we can include the ./sources as text in a way that makes sense. There are a LOT of files and the original concern was without the project linkage it really would not make sense.

    We do want to release a Xilinx LVDS design possibly late this year, but it is not ready unfortunately.

    I will give another update early next week.

    Regards,
    Brian
  • Thanks, Brian.

    I will wait for the source code. Before that I would like to know a simple thing: Can you tell me if both (ADC and DAC adapters) are  pin compatible with KC705 board?

    With which connector? HPC, LPC or both?

    Can you take those boards and try to insert both into the same KC705 board?

    If you could publish a picture of both inserted into this board, I'll be most grateful.

    Thanks for your support,

    Avi

  • Hello Avi,

    I was able to confirm the mechanical fit of the KC705 to the adapter boards and EVMs.  The adapter cards use the 'LPC' configuration of the FMC connector, so they are compatible with both FMC connectors on the KC705.

    There is a mechanical interference with a standoff and the DAC board.  You will need to remove a standoff. 

    Finally, the standoff heights must be adjusted.  The FMC and HSMC connectors perform well if the boards match height when mated, but mismatch can cause intermittent contact problems.

    I think the other concern about mismatch/interference has been addressed with a BOM change on the DAC board HSMC connector.  Please see this post for explanation. 

    https://e2e.ti.com/support/data_converters/high_speed_data_converters/w/design_notes/3316.dac348x-hsmc-connectors

    The board you order will have the correct connector on it.

    Regards,

    Brian

  • Avi,
    For the TIDA-00069 project are you able to download Quartus Prime Standard Edition ? I think you will be able to download and install then request a 30-day license to open and review the project. Please let me know if this is not the case.

    After the project has been un-archived you will be able to review the Verilog. As mentioned in the TIDA-00069 guide we have instantiated a few of the Altera IP blocks (megafunctions). You will need to build or find similar IP for the Xilinx device.

    Regards,
    Brian
  • I don't know how to work with that software. I also asked one of the designers who work with me to open this file and he said that he couldn't. Is it an old version? damaged file?
    I wonder why can't you ask the person who designed it to make a ZIP file of all text files (not QAR please!) and just put it on the forum?
    I'm sure that I'm not the only one who works with Xilinx. You got a very nice paper saying that those DACs works with Xilinx boards and yet, no support at all. I already posted few questions and none of them were answered properly.
  • Avi,
    I have found another resource that might be helpful. Xilinx has an XAPP866 literature and example project for interfacing with one of our Serial LVDS devices. It goes through the design process, and how to align the data.

    The ADS4249 would be configured as DDR (sample on both clock edges), so there would be some modification required, but it might be a more straight-forward port than the Altera code.

    The Literature and Project are available on Xilinx.com and search XAPP866. You will have to log in to Xilinx to download the code.

    Regards,
    Brian
  • Avi,
    We have restrictions on how software is released so I am not easily able to just zip source files and send them. Sorry about this.

    Were you able to review the XAPP866 project?


    Regards,
    Brian

  • Hi Brian,

    The XAPP866 application note is not applicable for me from the following reasons:

    1. They say: "Speeds of up to 125 Megasamples per second (MSPS)". ADS4249 is 250 Msamples/sec - quite a different timing.

    2. It is serial LVDS. My question was about Parallel LVDS which is used to connect TI boards to Xilinx boards.

    3. On serial LVDS the bandwidth is about 20 times higher. Do you think it would work with all of that distance between the ADC and the Xilinx board? (with TI adapter boards in the midle)
    I doubt it.

    I wonder about your argument about sending the source code that you already bublished in the QAR file on your web page.
    To publish a QAR project file (with al the source code inside) is OK but to publish the same as ZIP file is not OK?
    I really don't understand what kind of "restrictions" do you have...

  • Can you create a HDL project for those ADC and DAC such as ADI? check wiki.analog.com/.../xilinx
  • Hi Weihua
    The only FPGA platform that we have support for this DAC EVM is the TSW1400EVM. We don't have any HDL or other support for the KC705 and LVDS DACs.
    Best regards,
    Jim B
  • Jim,

    We know that and because of that we contacted TI and asked you to help us to start with Xilinx.

    But instead of helping us, you start telling us about policies and delay us with our projects.

    The other guy who responded to this inquiry with a link to Analog Devices tried to tell you that the preferable choice for customers who work with Xilinx is to buy from Analog Devices and not from TI.

    I asked that you will open the QAR file that you already publish and zip the VHDL code in TXT format and put them on the forum for me and other users.

    The answer was to tell me to download Altera's software and waste few hours to learn how it works and then extract the QAR file.

    This is what you call technical support?

    I'm sorry but I'm very disappointed.

  • Avi,
    We are not able to publish the direct VHDL because the design utilizes scripted Intel MegaCores in places. These configured cores are part of Intel's IP license and are not directly distributable without their license. Without these cores and their context the design would not make sense so we require you to install Quartus to view.

    The referenced Xilinx project was offered as a high-level architecture example, not as a 1-to-1 at speed working prototype. Sorry for the confusion.

    We plan to release further reference designs (Xilinx and Intel) in the future but I cannot offer any timeline at this time.

    Regards,
    Brian