Dear
I have reviewed the below blog post and some TI's high speed application notes.
but most of the PCBs they have used have many layers.
I have a 4 layers PCB with dielectric constant 4.2.
the board thickness is 63mils (1.6mm).
the stack-up is as follow:
L1 (1.4mils)
d=7mils
L2 (1.2mils)
d=44mils (or 28 mils or 20mils)
L3(1.2mils)
d=7mils
L4 (1.4mils)
I have implemented some 3.125Gbps LVDS vias from L1 to L4.
could you please give me a suitable via size to have 100 Ohm impedance?
Thanks