Other Parts Discussed in Thread: ADC12DJ3200,
Hello,
We are while setting up the demo for the TI-ADC12DJ3200EVM kit with Xilinx KCU105 board using the UHWD_2016.3 bit files we are seeing poor results.
We are seeing the very Noise floor at -50dBFs, and secondly the frequency folding is happening for the targeted frequency.
The JMODE0 is used by the ADC12XXXGUI and the settings and setup as described in the SLAU711 were correctly followed.
Setup info: ADC12DJ3200 EVM with Xilinx KCU105 EVM( Both static & DHCP Ethernet modes)
ADC sampling rate: 1600MSPS , output data rate: 3200MSPS.
ADC in JMODE0
The noise floor remains at the same level even without the input signal connected to ADC input.
Individually the ADC and the Xilinx KCU105 Eval kit work and show proper results for the JESD204 interfaces when tested with other demos.
However when together interfaced we observe the above issue.
Appreciate for feedbacks/suggestions/advises.
Thanks and Best Regards,

