This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC32J45EVM: ADC don't work with CLK_in 200 MHz and CLK-DIV=2

Part Number: ADC32J45EVM
Other Parts Discussed in Thread: LMK04828

Hello,

I have a test setup using your ADC32J45EVM with your TSW14J50, using the ADC3000 SW to configure the ADC and LMK and using the high speed data converter pro software to analyse the ADC.

In some configurations I have Problems to establish the JESD-Link.

If I use an ADC input clock of 320 MHz I can use the clk divider inside the ADC to reduce the sample rate but when I reduce the ADC input CLK by increasing the clock divider of the LMK output it stops working.

I only have these Problems when I am using the ADC internal clock divider. It works just fine when I am not using the clock divider.

On my own hardware I have a 200 MHz clock and want to run the ADC with 100 Msps so I need the internal clock divider to work at that frequency.

I attached two configuration with the settings I used to run my 200 MHz /100 Msps setup. the first is without the ADC clock divider which works fine and the other one is wth the ADC clock divider set to 2 which I can't get to work.

Thank you for your help!

best regards

Torsten Bandel

200M_with_clk_div_2.cfg200M_without_clk_div.cfg

  • Torsten,

    We are looking into this and will get back to you soon.

    Regards,

    Jim

  • Torsten,

    I was able to duplicate your issue. I have sent this off to the design team to get their inputs regarding this.

    Regards,

    Jim

  • I have also done further investigations.  The only frequencies I can get the JESD-Interface to synchronize with the clock divider enabled is around 320 MHz and 160 MHz.

    I have done a spectral measurement of the JESD data lane and compared different setting of input frequency and clock divider.

    It seems like there is a lot of noise when I enable the clock divider at certain frequencies. More info in the attachment.

    regards,

    TorstenADC_clk_div_JESD_data_Spectral_measurment.docx

  • Torsten,

    Since there has not been any activity regarding this post in awhile, I am closing it.

    Regards,

    Jim
  • I am still waiting for a reply from your side.

    You said you can reproduce the problem and forwarded it to your design team.

    The problem still exists and I would still like to know if it is a configuration problem or is it an design problem?

    is there any workaround  where I can youse the clock divider at 200 MHz?

    I use a 100 MHz clock at the moment but because of this my overall design perfomance is worse.

  • Torsten,

    You have register add 0x27 set wrong in your divide by 2 config file. This needs to be set to 0x80 and not 0x00.

    Regards,

    Jim

  • Torsten,

    I had a mistake with my original setup. There was no problem. I am able to operate in this mode with no problem.

    Regards,

    Jim

  • Hi Jim,

    I found the problem but I do not understand it properly.

    I need to set SYSREF to periodic clock to function in subclass 0.

    as far as I understand, SYSREF is necessary for aligning the LMFC in subclass 1 and is just sampled by the sample clock. Thus I thought I can neglect it in subclass 0.

    Can you please tell me why I need the SYSREF signal for the clock divider and is it sufficient if I just connect my clock to it for subclass 0 operation?.

    Thank you in advance.

    Regards,

    Torsten

  • Torsten,

    This part needs SYSREF to reset the SPI state machine. 

    Regards,

    Jim  

  • sbaa221.pdfTorsten,

    Actually I found out you can create a software SYSREF to allow operation in subclass 0 without using an external SYSREF signal. See the attached app note for more information.

    Regards,

    Jim

  • Does this also work with theADC32J45? I cannot find the respective registers in the datasheet of the 32J45, I can only find this for the 32RF45.

    Is there another way to operate without the regular SYSREF signal? Like applying clock to SYSREF or pull up/pull down? Otherwise, it would cost me an additional clock divider or an far more complex clock synthesizer like the LMK04828 which I would like to avoid.

    Regards,

    Torsten