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DAC8871 Output Filtering

JACR
Intellectual 270 points
Other Parts Discussed in Thread: DAC8871, OPA277

 

Hi people

Im working on the design of two channel bipotentiostat/galvanostat and im going to use the DAC8871 as a signal generator (voltage ramps basically) because of its capability of working with different dual references (which means different spans of generation)

The thing is... what is the best output filtering i should use with this device?  Is it a passive filter or an active filter (my solution would be a 2nd order sallen key with 1kHz) but i dont know how much will this affect the accuracy of the system... or if i should use only an ompamp buffer as suggested on the datasheet (with an opa277)

I have another question about the major carry glitch; if im understanding the datasheet correctly... i will only have the glitch when im using the "enable" LDAC?  If im not using it (if i have it tied low), then i dont have to worry about the major carry glitch (i know it will be there... i just want to know if it will be smaller and how much)

 

Thank you very much for your time and your answers

 

 

  • 0
    TI__Mastermind 43915 points

    Hi JACR,

    First off let me explain the major carry glitch. The main source of the major carry glitch in the DAC8871 is coming from switching synchronization internal to the DAC's internal R2R structure. It does not rely on the /LDAC pulse and will still be present regardless of whether /LDAC is held low or not. /LDAC is used as to signal when you would like the DAC to be loaded with the data word that is currently in the input shift register.

    The DAC8871 is an unbuffered R2R DAC meaning that you are going to need an op amp at the output to drive whatever load you would like while isolating the R2R resistor structure from your output. As far as post filtering, having a first or second order filter with a 1KHz roll off frequency is going to help with the DAC glitching. It is, however, going to increase your DACs settling time. Using a second order filter vs a first order filter will settle faster but will increase the settling time of the overall system. This is just something to keep in mind as this is going into a signal generating application. Do you mind posting a schematic of your sallen key filter that you would plan to use?

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Intellectual 270 points

     

    Hi Tony, and thanks a lot for the answer, now i have everything clear about the major carry glitch on the DAC8871.

    However, since i will be using the DAC8871 to generate signals in DC and low frequencies, i think the increased settling time of the DAC will not be an issue. The sallen key i was thinking would use the standard configuration and would be implemented using the OPA277 as a butterworth filter with FSF=1 and Q=0,7071

    One last question, if the amplitude of the glitch is the problem (probably major carry and 1/4 scale) would it be better to use the 2nd order filter? or a 1st order filter (even a passive one) will do the trick.

    Once again, thank you very much for your time and your answers

     

     

  • 0 in reply to JACR
    TI__Mastermind 43915 points

    Hi JACR,

    The way that I understand it, you plan to have a post DAC filter for two reasons; to help smooth out the code to code step transitions, and to help attenuate the amplitude of the major carry glitch. Using our FilterPro program and TINA spice, I was able to simulate the output behavior of using a first order RC filer vs. a second order Sallen Key to help with one of your two concerns. I was able to simulate the code to code steps to give you an idea of how filtering would smooth out the transitions but was unable to simulate the glitching behavior. I know using a Sallen Key filter will also help attenuate the glitch but I am not sure how much in comparison to a first order RC. I put my findings together in the attached Word document so you can see the setup and the results using TINA models. If you would like, I could send you the TINA file and you can play around with it to get the design as you would like.

    Regards,

    Tony Calabria

    SallenkeyvsRC.doc
  • 0 in reply to Tony Calabria
    Intellectual 270 points

     

    Hi Tony... ty very much for your answer and it was pretty clear as usual.

    Yes, i would like to have the TINA file and spend some time getting to know the device in depth.  I have to say that this is even better than writing to support because you get in touch with the best design engineers in the world.

    Thank you very much and best regards

    P.S  The code to code smoothing is pretty visible and i think that i will work a combined scheme to deal with the major carry glitch (first, i think i have to implement the SK filter and i guess i can probably wait some ns or even us before i update the output on labview because im working in low frequency... i can even average the output for the major carry glitch and 1/4 and 3/4 scale)

     

  • 0 in reply to JACR
    TI__Mastermind 43915 points

    Hi JACR,

    I attached the TINA file I used to make these simulations for you. You will notice that I have this macro labeled PWL I used to create the staircase. If you open up that macro, you will see that you can create any waveform that you would like. So, essentially if you can get an idea of exactly how the glitch looks in your system, you could reproduce the glitch signal in TINA to see how the circuit attenuates the amplitude.

    Regards,

    Tony Calabria

    salenkeyvsRC.TSC