Other Parts Discussed in Thread: ADS1278, TMS320C6748, ADS1271
We are interfacing an ADS1278 to the C6748 using the McBSP1 port. We are running BIOS 5.41.10.36, and are also using the PSP 1.30.01 mcbsp driver with edma3 support. According to the ADS1278 data sheet the recommended circuit for connecting the ADS1278 to the McBSP uses the same clock for SCLK and CLK, with a flip flop to reclock the data. We require a 50 KHz sample rate and high resolution, so the input clock must be 25.6 MHz (the divide ratio is 512). So, the serial data rate is also 25.6 MHz which means there are 512 data bits per Frame Sync going into the McBSP. The ADS1278 has 8 channels and each sample is 24 bits. There is no daisy chaining, so we only need 192 bits of data.
Can the McBSP driver be configured to generate a 50 Khz Frame Sync rate, 25.6 MHz CLKR, and only load and store 8 channels 24 bits/sample? The CPU clock will be 294.4 MHz (created from a 25.6 MHz crystal).
I was thinking that I could set it up for dual phase, where Phase0 would have 8 words with a word length of 24 (192 bits). Phase1 would have 10 words with a word length of 32 (320 bits). This would give 512 bits per frame, making CLKR = FSYNC x 512. The ADS1278 would generate the first 192 bits from the A/D data then would just send the value of DIN after that. Can I use the multichannel support to ignore Phase1? How would you set the parameters for that?
Thanks,
Mary
Below are the structures used to setup the McBSP driver. These are taken from the McBSP driver example code.
/**< settings to configure the TX or RX hardware sections
* Referred to in mcbsp.tci by device drivers
* See Mcbsp.h for typedefs
*
*/
Mcbsp_DataConfig mcbspChanConfig =
{
Mcbsp_Phase_DUAL, /**< Phase of the McBSP data stream */
Mcbsp_WordLength_24, /**< Length of the data word in first phase */
Mcbsp_WordLength_32, /**< Length of the data word in second when dual phase is selected */
8, /**< Length of the data frame in first phase */
10, /**< Length of the data frame in second phase */
Mcbsp_FrmSync_DETECT, /**< Frame sync ignore bit */
Mcbsp_DataDelay_1_BIT, /**< Data delay to be configured in number of Bits */
Mcbsp_Compand_OFF_MSB_FIRST, /**< companding selection */
Mcbsp_BitReversal_DISABLE, /**< Transmit 32-bit bit reversal feature enable bit. */
Mcbsp_IntMode_ON_SYNCERR, /**< Event for which the interrupt is to be generated */
Mcbsp_RxJust_RZF, /**< Receive sign extension and justification settings (RX only setting) */
// Right justified, zero fill
Mcbsp_DxEna_OFF /**< High impedance enable/disbale bit for the DX pin (TX only setting) */
};
/**< clock setup for the TX section */
Mcbsp_ClkSetup mcbspClkConfig =
{
Mcbsp_FsClkMode_INTERNAL, /**< Frame sync mode bit (FSXM/FSRM)(Internal/External)*/
50000, /* 50KHz Frame Sync Frequency */
Mcbsp_TxRxClkMode_INTERNAL, /**< Bit clock mode (internal or external) */
Mcbsp_FsPol_ACTIVE_HIGH,
Mcbsp_ClkPol_RISING_EDGE
};
/**< Multi channel setup */
Mcbsp_McrSetup mcbspMultiChanCtrl =
{
Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED,
Mcbsp_PartitionMode_CHAN_0_15,
Mcbsp_PartitionMode_CHAN_16_31,
Mcbsp_PartitionMode_2
};
Mcbsp_ChanParams mcbspChanparam =
{
Mcbsp_WordLength_24, /* wordlength configured */
NULL, /* loop job buffer internal */
0, /* user loopjob length */
NULL, /* global error callback */
NULL, /* edma Handle */
1, /* EDMA event queue */
8, /* hwi number */
Mcbsp_BufferFormat_MULTISLOT_INTERLEAVED,
TRUE, /* FIFO mode enabled */
&mcbspChanConfig, /* channel configuration */
&mcbspClkConfig, /* clock configuration */
&mcbspMultiChanCtrl, /* multi channel control */
0x00, /* channel enable masks */
0x00,
0x00,
0x00
};
