This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
The ADS1258 has only one data register, which gets updated with the result of the last conversion completed. Updates are held off while you're reading the register, but conversions continue. If you're reading channel 1, for example, and taking your time doing it, it's quite possible that conversions for channel 2 and 3 happen before you're done - and so the next channel you read is channel 4, etc. This is the usual explanation for complaints of the ADC output not matching the inputs - check your timings and see.
At the 23ksps data rate, your SCLK would need to be at a minimum 5MHz, and that would only give you enough time to read one channel after the other (your processor wouldn't have time to do anything with the data). So you need to make sure that your SPI clock frequency is fast enough to support reading the data out fast enough and leave you time to do other things.
We don't have any example code using the ADS1258 with an MSP430, but we do have some for some of our DSPs, If you're interested in that, let me know and we can point you to that.
Babuddin,
I attached the example for the ADS1258 and the TMS320VC5510 to this post for your reference. As for your clock speed, I don't expect any problems for the communication with the ADS1258 at 16MHz, so you should be fine here.
Regards,
Richard
Babu,
I must correct my previous answer - I gave you some numbers that I remembered off the top of my head but those apply to a completely different set of operating conditions. So, let me attempt to straighten this out:
First off, the ADS1258 SCLK cannot be more than 1/2 of the system clock, which is usually somewhere around 16MHz - so the upper limit on the SCLK frequency is 8MHz (I think Richard forgot this in his message to you).
In auto-scan mode, the ADS1258 operates with a maximum data rate of 23739Hz - meaning that DRDYs will come at you every 42us or so. You need to read all the data out for one channel within that 42us window. The simplest way to do this is in Channel Data Read Direct mode, so you don't have to send any commands. If you elect to not send the Status byte, then you must clock out 24 bits within this window, allowing an SCLK as slow as 570kHz - let's say then that the lower limit is 600kHz.
If you do send the status byte, then there's 32 bits that need to be clocked out during this time, which requires an SCLK of at least 760kHz - so let's just say it's 800kHz.
So the right way to look at this is your SCLK must be between 600kHz (or 800kHz if sending Status bytes) and 8MHz in order to capture all the channels without losing any channel data, in the simplest of data collection modes. If you are doing more things between channel reads, (like needing to send commands and such), obviously the SCLK rate must be higher than the minimums I've suggested here.
RIchard has provided you with some code examples, so hopefully that will help out.
Rick Downs said:The ADS1258 has only one data register, which gets updated with the result of the last conversion completed. Updates are held off while you're reading the register, but conversions continue. If you're reading channel 1, for example, and taking your time doing it, it's quite possible that conversions for channel 2 and 3 happen before you're done - and so the next channel you read is channel 4, etc. This is the usual explanation for complaints of the ADC output not matching the inputs - check your timings and see.
At the 23ksps data rate, your SCLK would need to be at a minimum 5MHz, and that would only give you enough time to read one channel after the other (your processor wouldn't have time to do anything with the data). So you need to make sure that your SPI clock frequency is fast enough to support reading the data out fast enough and leave you time to do other things.
We don't have any example code using the ADS1258 with an MSP430, but we do have some for some of our DSPs, If you're interested in that, let me know and we can point you to that.
Hi,
I'm using the ADS1258 with the following configuration:-
Freq = 16Mhz
CONFIG0 = 0x1A (CLKENB = 1, STAT = 1, BYPAS = 1)
CONFIG1 = 0x30 ( Delay = 11b, SensorBiasCS = 0, DataRate = 0)
MUXSCH = 0x00
MUXDIF = 0x00
MUXSG0 = 0xFF
MUXSG1 = 0xFF
SYSRED = 0x10 (GAIN = 1)
GPIOC = 0xFF
GPIOB = 0x00
My preferred method of acuiring the channel data is using the DRDY signal to generate an interrupt and read the channel data in an interrupt routine, but I am unable to do this at the present time.
In the meantime I was hoping to use the NEW bit mechanism, using the "Channel Data Read Command(Register Format) " with the MUL bit set.
Your comment "The ADS1258 has only one data register" may explain some of the problems I have been experiencing.
I was assuming that I could wait a period of time (>10ms for my config, the time at which all 17 channels would have captured data) before reading all the channel data. I had thought there was a data register associated with each individual channel. Could you confirm this is not the case and that there is only one data register shared by all channels.
If this is the case, am I correct in thinking that I should read the the data at a rate that is faster than the capture rate so that I so not miss any channel data. With my configuration (17 channels, DRATE=0) each channel data is captured every 560us, so I should poll the NEW bit faster than 570us.
Regards,
Pete
Channel Data Read Command (register format) with te
Peter Scullion said:Your comment "The ADS1258 has only one data register" may explain some of the problems I have been experiencing.
I was assuming that I could wait a period of time (>10ms for my config, the time at which all 17 channels would have captured data) before reading all the channel data. I had thought there was a data register associated with each individual channel. Could you confirm this is not the case and that there is only one data register shared by all channels.
If this is the case, am I correct in thinking that I should read the the data at a rate that is faster than the capture rate so that I so not miss any channel data. With my configuration (17 channels, DRATE=0) each channel data is captured every 560us, so I should poll the NEW bit faster than 570us.
I can confirm that there is but one data register in the ADS1258, shared by all channels. That means you must retrieve data after each channel is converted, so yes, to avoid losing data, you must be able to read the data out before the next channel's converted data will be available.
I accept that that there is but one data register. BUT with that in mind I am hard pressed to understand how one is expected to use this device in autoscan mode. In my experimentation I see that if one channel is selected and conversion is enabled with the START pin the DRDY goes active in about 43 microsecs - ok, that's no surprise. But if sixteen channels are selected and conversion is enabled with the START pin the DRDY goes active in about 700 microsecs - again no surprise - after all, 16 times 43.75 does equal 700. This leads me to believe though that all 16 channels were converted. But the dilemma is: I can only get the value from the last channel converted (AIN15)?!! Why would the device convert 16 channels when only one can be read?!
With these results in mind I do not understand the above statement: "you must be able to read the data out before the next channel's converted data will be available" How does one do that when DRDY only comes out at the very end of all conversions?
This is really starting to smell like, even though multiple channels can be selected, that no matter what mode is used or how many channels are selected the execution must be one channel converted followed by that channel being read. So then, even for multiple channels selected in autoscan mode the conversions must be pulsed so that only one conversion is executed.
Please show me the error of my thinking.
Charlie -
The converter should be issuing a low pulse of DRDY when each channel data is ready. In that if you have multiple channels selected for the autoscan, you should receive a low DRDY for each channel of data.
The details for this are discussed on page 28 of the datasheet located at http://focus.ti.com/lit/ds/symlink/ads1258.pdf.
The DRDY pulse is issued at the completion of a conversion and the channel counter is incremented to the next selected channel. If the end of the channel selection is reached, the conversion continues at the beginning of the selection until the START signal is removed (low). If the processor is not ready when the data is ready, you may miss data since the converter is already converting the next channel and will output this data (instead of the previous data that you had been expecting).