ADS1120 Configuration registers setting problem

Kazuhiko Ogawa

Other Parts Discussed in Thread: ADS1120

Hallo,

Our customer has a problem with the configuration registers setting in the ADS1120.
They are setting up as the following pseudo code example in the ADS1120 datasheet.

Power-up;
Delay;
Configure the SPI interface of the microcontroller to SPI mode 1 (CPOL = 0, CPHA = 1);
If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an output;
Configure the microcontroller GPIO connected to the DRDY pin as an interrupt input;
Set CS to the device low;
Delay;
Send the RESET command (06h) to make sure the device is properly reset after power-up;
Write the respective register configuration with the WREG command (43h, 08h, 04h, 10h, and 00h);
Delay;
As a sanity check, read back all configuration registers with the RREG command (23h);

But, they have always read “ FFh FFh FFh FFh “ or “ 0Fh FFh FFh FFh “.
Has this device broken?
Do they mistake the setting procedure? ( Is there NOP command or something? )
Would you please advice me?

Best Regards,
Kazu Ogawa

over 11 years ago

0 Bob Benjamin over 11 years ago

TI__Guru** 113765 points

Hi Kazu,

The process given should work. You can use 0xFF as a NOP. Is the CLK pin grounded on the ADS1120 or is an external clock being used? What is the SPI SCLK frequency?

Can you send me a schematic, or at least identify how all the pins of the ADS1120 are connected? Do you have scope/logic analyzer shots of the communication you can send me? Which device package is being used?

Best regards,

Bob B

0 Kazuhiko Ogawa over 11 years ago in reply to Bob Benjamin

Intellectual 985 points

Bob-san,

Thank you very much for your reply.
I received a message from the customer today.
He mentioned,
When SPI SCLK speed is,
   tSCLK=250NS, NG(all 0)
   tSCLK=500NS, NG(sometimes NG)
   tSCLK=1uS, OK
The problem seems to be caused by the SPI SCLK frequency.

He has the questions.
1. How much is actual maximum frequency of the SPI SCLK?
2. How long is the recommended acceptable delay time of “ Delay,“ in Pseudo Code Example of the datasheet?
Could you please let me know?

Best Regards,
Kazu Ogawa

0 Bob Benjamin over 11 years ago in reply to Kazuhiko Ogawa

TI__Guru** 113765 points

Hi Ogawa-san,

The period of the SCLK should work at 250ns period. It would be helpful to be able to see scope/logic analyzer shots of the communication. All timing requirements must be met including the timing from CS going low to rising edge of SCLK (which is a minimum of 50ns). Maximum SCLK frequency relates to the inverse of the minumum SCLK period (150nS) which is about 6.6MHz.

One issue that can take place with a fast SCLK is capacitance in the signal path. I would suspect that this may be the problem and the command does not get properly decoded. Capacitance in the clock line can create issues when the clock no longer looks like a square wave, but rather more exponential in shape (such as a charge discharge across the cap) which then violates the minimum pulse width high (or low) dwell times of 60ns. Slowing the clock would change this condition so that there is a longer period of low and high dwell time of the clock. The customer should be able to see this by probing at the ADS1120 pins (or as close as possible to the device inputs).

As far as the 'Delay' time shown in the psuedo code, this does not necessarily need to be the same length of time for each portion of the code where it is shown. A delay time of 50us should cover most cases. See the section on 'Reset and Power-Up' on page 31 of the ADS1120 datasheet.

Best regards,

Bob B

0 Kazuhiko Ogawa over 11 years ago in reply to Bob Benjamin

Intellectual 985 points

Bob-san,

Thank you very much for your answer.

I will give the customer your advice.

Best Regards,

Kazu Ogawa

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ADS1120 Configuration registers setting problem