DAC7750 - Is it possible for the device to take action on its input shift register contents without seeing a rising edge on LATCH if a particular pattern is present on DIN and SCLK.

Michel Sirois

Other Parts Discussed in Thread: DAC8760, DAC7750

We use two DAC7750 configured in daisy chain mode. They share the SPI bus with an external SPI flash. The problem occurs when the pattern 0x57, 0x58, 0x59 is sent to the external flash (without any rising edge on the LATCH input of the DAC). In this case, the first DAC of the daisy chain stops working correctly as if its configuration register was corrupted. A software reset of the DAC or a reconfiguration of the configuration register seems to bring back the DAC in a normal process. I found an errata pretty similar to this one but with the DAC8760 (See https://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/403318).

Could someone confirm me that this is the same kind of problem and what the proposed work-around are.

Another question. Is it possible to use two DAC7750 on the same SPI bus but not configured in daisy chain mode? This is not clear in the datasheet. I suspect that the same kind of problem could happen.

over 10 years ago

0 Michel Sirois over 10 years ago

Prodigy 30 points

Sorry, I've put the wrong link for the errata. Here is the good one e2e.ti.com/.../3153.watchdog-timer

0 Eugenio Mejia over 10 years ago

TI__Genius 10615 points

Hi Michel,

It seems your are writing to reserved bits in the configuration register (0x57).

If you take a look at Table 13 on page 36 of the DAC7750 datasheet, you will see that only the last six bits should be written to on register 0x57. Writing to these registers can cause undesired behavior.

Please let us know if this resolves your issue or if you have any other questions.

0 Michel Sirois over 10 years ago in reply to Eugenio Mejia

Prodigy 30 points

Hi Eugenio,

Thanks for the fast reply.

In my case, the firmware never access this register. The problem is that this register (0x57) is modified even if I do not perform a rising edge on the LATCH pin of the DAC. The data are intended to another SPI device (on the same SPI bus), but the DAC7750 catches them without rising edge on the LATCH. This is not normal. Please take a look at this errata from a similar chip (e2e.ti.com/.../3153.watchdog-timer). Could it be the same problem ?

Thank you
Michel

0 Eugenio Mejia over 10 years ago in reply to Michel Sirois

TI__Genius 10615 points

Hi Michel,

It seems with the holiday delays I missed this post.

It is possible to activate the watchdog timer or the CRC erroneously due to a glitch on the current revision of the device. Please take a look at the links for some possible work-arounds.

If you still have any questions please let me know.

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DAC7750 - Is it possible for the device to take action on its input shift register contents without seeing a rising edge on LATCH if a particular pattern is present on DIN and SCLK.