ADS8353 DIFFERENCE BETWEEN READ OPERATION OF USER PROGRAMMABLE REGISTER & CONVERSION RESULT

PRIYANKA VIRKAR

Other Parts Discussed in Thread: ADS8353, ADS7253, ADS7853

Hi,

If it is necessary every time to write cfr while reading conversion result for single mode(32-CLK, single-SDO mode).
How much clock falling edge required to read conversion result (32-CLK, single-SDO mode)? Also to read cfr register.
If falling edges of clock (specified for every operation as per data sheet) are must ? Is there any alternate to Falling edges of clock.

over 9 years ago

0 Luis Chioye over 9 years ago

TI__Guru 55466 points

Hi Priyanka,

The ADS8353 (16-BIT) version can be configured on 32-CLK interface with Single or Dual-SDO mode. The ADS8353 (16-Bit) version requires at least 32 SCLK’s in Dual-SDO mode; and 48 SCLK’s in Single-SDO mode with a max SCLK frequency of 20MHz.
It is not necessary to write the CONFIG register on every conversion. If the Single–SDO mode is required, the user needs to write the CONFIG register at Power-up using a 32-CLK frame. In order to read both channels configured with Single-SDO, you will require 48-SCLKs as shown on Figure 92.

The other devices in the family, ADS7853 (14-B) and ADS7253 (12-B) support an additional option for 16-CLK interface with Single-SDO or Dual–SDO mode.

If possible, Can you please let us know the details of your application requirements, such as sampling rate, resolution? Is simultaneous sampling required? What is the end application?

Thanks and Regards,
Luis

0 PRIYANKA VIRKAR over 9 years ago in reply to Luis Chioye

Prodigy 30 points

Hi
Thank you for reply.
what about user programmable register read operation?
Is there any alternative for falling edges of clock, As it keeps application busy for that period & time consuming?

Data converters

Data converters forum

ADS8353 DIFFERENCE BETWEEN READ OPERATION OF USER PROGRAMMABLE REGISTER & CONVERSION RESULT