Other Parts Discussed in Thread: REF5050, DAC9881
This thread is an extension of this:
Where we had some problems with the connectivity of this EVM.
I ran through the user guide, SLAU279A (www.ti.com/lit/ug/slau279a/slau279a.pdf), and found a few points that seem to be inconsistent. So I am listing them here so it may help other people working with it.
I kindly ask for someone from TI to confirm, and if deemed to be relevant, perhaps forward these information to document revision.
1.2.2) (...) The reference voltages, VREFH and VREFL are selectable via jumpers W8 and W4. When shorting pins 1 and 2 of both jumpers, the onboard +5-V reference via REF5050 is selected. Shorting pins 2 and 3 of both jumpers selects the reference voltages that are applied via J4 pins 18 and 20, respectively.
Note: That is false for W4. According to Table 7. Jumper Setting Function and physical measurement, W4 must be set to 2 and 3 to set VrefL to gnd (same gnd of MMB0 and DAC).
5.1 Factory Default Setting. Table 2. Factory Default Jumper Setting
W5 1-2 Negative supply rail of the output operational amplifier, U2, is powered by VSS for bipolar operation.
Note: Worth noting that there is no pin number marking on the mask layer for the W5 element. So one would normally assume that pin 1 is on the left, according to all other horizontal headers/jumpers. However, W5 is turned! Pin 1 is on the right, and 3 on the left side of the board. The very discrete and hard to see corners on the mask layer are not really noticeable.
Although the text is right, the position is tricky. Jumper position 2-3 is correct for unipolar, gnd operation, and NOT bipolar operation (as stated). Now that means shorting the first and second pins of W5, from left to right. Same for diagram on 5.5 Jumper setting. Also, on my EVM, W5 came opened.
W10 OPEN The LDAC signal of the DAC9881 is tied to ground for synchronous update of the DAC9881 output.
Note: In my board, it came shorted. Luckily, the J1 jumper was also incorrectly opened. It seems like someone was doing some tests driving the /LDAC/ via software.
I do hope that if this mistake on W10 happens to someone else, and J1 1:2 comes shorted, the driving pin coming from the MMB0 board is set to 3state... or this pin won't be with us much longer...
J1 1-2 The LDAC signal of the DAC9881 is tied to ground for synchronous DAC update operation.
Note: On my EVM, it came opened, and that means that the /LDAC/ pin is pulled up to IOVDD by R15 (see schematics on pg 20). J1:1 is routed to DAC9881 /LDAC/ pin 3, and J1:2 is gnd.
