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ADS9110: RVS pin behavior during Zone2 SRC-mode transfers

Vikram Godbole
Prodigy 90 points
Part Number: ADS9110

The RVS pin on this part is overloaded to provide the internal ADCST as well as to provide the clock in SRC mode transfers. What is the behavior of RVS if we are doing a SRC transfer in Zone2 mode? 

RVS will go low in response to CONVST. If we now pull CSn low to do a data transfer (after Td_cnvcap), RVS will start toggling within 40ns per datasheet Fig 6. After the transfer is done, if we pull CSn high, RVS is expected to return high within 70ns per that same timing diagram. However, if the conversion is still in progress, RVS is expected to be low for Tconv_min=300ns (datasheet Fig 43). So in this case, will RVS return high (following CSn deassertion) or stay low (till conversion is done)? 

What happens if the data transfer is happening during the Tconv_min to Tconv_max window where RVS is expected to go high? Does the data transfer timing/behavior take precedence over the conversion process timing/behavior for the RVS pin?

 

  • 0
    TI__Expert 3675 points
    Hi Vikram,

    The RVS pin is a multi-function pin which can indicate the ADC conversion status (ADCST) as well as be a part of the digital interface.
    In normal SPI (00/01/10/11) operation, the RVS pin can be used determine end-of-conversion (EOC).

    To answer your first question -
    When CSn = 1, RVS reflects ADCST signal, irrespective of the data transfer mode selected. Hence, during an on-going conversion, if CSn is pulled high RVS will stay low until EOC.

    To answer the second question -
    CSn = 0 takes precedence over RVS behaviour, irrespective of ADC activity. Hence between Tconv_min to Tconv_max window, just as anywhere else in the data transfer frame, RVS will operate as per the data transfer timing diagram.

    To add some more notes about the Enhanced-SPI module - this interface module is independent of the ADC. This means, you could be reading data (from a previous conversion) while the ADC is converting the sampled voltage. This is the reason why, CSn = 0 takes precedence over RVS behaviour during an ongoing conversion.
    When CSn = 1, the SDOs are tristate and hence RVS returns to indicating EOC status.

    You can find more details about the Enhanced-SPI interface in this white paper - www.ti.com/.../sbay002.pdf
  • 0 in reply to RahulVK
    Prodigy 90 points

    Thanks Rahul, this clarifies my questions. 

    I have one more: the document you linked mentions two quiet zones during which it is required that there be no activity on digital output lines. Unless I've missed it, the ADS9110 datasheet warns against only the first of the two (around the CONVST pulse). Does an EOC "red zone" exist for this ADC?

  • 0 in reply to Vikram Godbole
    TI__Expert 3675 points
    Hi Vikram,

    Thanks for confirming that your previous questions were answered.

    The white paper is generic in nature and discusses the interface aspect independent of the ADC implementation. The reason a read zone (quite zone) is shown near EOC is because LSB level decisions are being made.

    However, in the ADS9110, having a quiet time around CONVST pulse, as specified in datasheet, should suffice.

    Could you kindly share your use case (which interface mode and what are the system level constraints)?
    Thanks!
  • 0 in reply to RahulVK
    Prodigy 90 points

    Great, thanks.

    The ADC is interfaced to an FPGA, and intended for use at 2 MSPS. Interface mode is source-synchronous, quad SDO, DDR.