Other Parts Discussed in Thread: ADS1298, ADS1294, ADS1296
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Hi Ryan,
Thanks for your reply. We tried checking using a DSO and found DRDY was toggling with respect to DOUT when data is getting transmitted while we applied a test signal through the software. However, when we upload the above code, we found that during the transmission of the channel bytes through SPI, DRDY was toggling in between and doesn't seem synchronized, i.e it isn't latched to high during transmission and low otherwise. Also the header bytes do not recur properly after every 24 bytes. Is there a problem with the SCLK synchronizing with the internal clock? What are the necessary register configurations that need to be made to get the required number of samples through RDATAC mode?
Hello Vaibhav,
You cannot allow for /DRDY to transition high-to-low while you are reading data in RDATAC mode. The data in the output shift register will immediately be overwritten with new data. Remember that /DRDY is not latched - after the /DRDY falling edge, the first SCLK falling edge will force /DRDY to clear and return high.
SCLK and CLK do not need to be synchronous. In fact, the SPI interface in the ADS1299 is an asynchronous interface. The intention is for you to monitor the status of the /DRDY pin with a GPIO. When /DRDY goes low, the MCU should enter an interrupt service routine (ISR) to collect the data. This involves bringing the /CS pin low, toggling SCLK until all data is received, and bringing /CS high again. The ISR must be completed before the next conversion is ready (i.e. before the next /DRDY falling edge). The period between consecutive /DRDY falling edges will be equal to the configured data rate.
If you cannot read the data fast enough, you must either reduce the data rate or increase the SCLK frequency. Alternatively, RDATA mode allows you to read the most recent conversion result on demand by sending the RDATA SPI opcode whenever you wish to read data.
Best Regards,