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Original question:

ADS8339: Strange input pin offset

ADS8339: High Sample Rate missing bits

rjb
Intellectual 470 points
Part Number: ADS8339

Hello

I am using ADS8339 in 3 wire mode at 240ksps conversion rate with Vref 2.5 Volts, with 5MHz SPI clock for data out.

Problem :  I am not able to obtain all the bits from ADC for 0 volts first 11 bits of MSB are 1's and rest 5 are zero.

As I reduce the SPI clock to 1MHz. I able to get correct data from but (15-bits only). 

As soon as I go above that in integer multiples of 1MHz rate It starts loosing LSBs.

Question :

1. I am not sure why this is happening. Not sure Why am I not able to get 16 bits, Please help.

Here's the schematic if that helps.

Thanks,

Rahul

  • 0
    TI__Mastermind 24940 points
    Hellow Rahul,

    Would you provide a scope shot of the digital communications, including CONVST, SDO, SCLK? This will help verify and debug any timing issues.
    The analog input is driving C7, if this capacitor is shorted, are the conversion results correct? After shorting the capacitor, you can use a known DC input and compare the conversion results.
    Is this capacitor, C7, needed to AC couple the input signal? Want to make sure the input signal is being conditioned as needed, what is the expected input signal frequency?

    Regards
    Cynthia
  • 0 in reply to Cynthia
    Intellectual 470 points

    Hello Cynthia,

    I currently don't have access to my hardware. I will update as much information asap.

    Can you please give me quick reference guides for the following.  Which I couldn't find in the datasheet.

    1. I want to obtain data at 250 ksps. What is the required SPI clock frequency ?

    2. What is the relation between SPI clock and Sampling rate ?

    Guide http://www.ti.com/lit/ug/sbau233a/sbau233a.pdf page 13 Comments on Data Rate  as following

    "" With SCLK frequency at 25-MHz, set data rate to a value from 6.105-KSPS to 250-KSPS.

       With SCLK frequency at 400 KHz, set the data rate to a value from 3.960-kSPS to 21.052-kSPS.""

    3. How to do the above? How can different data rates with the same SCLK ? Is it telling to skip the samples ?

  • 0 in reply to rjb
    TI__Mastermind 24940 points

    Thanks, that will be helpful.

    The data needst o be clocked out during the aquisition phase.

    At max sampling rate, 250Khz, the conversion phase will run at its maximum, 3300ns, leaving 700ns for the aquisition phase; the data needs to be clocked out during this 700ns aquisition phase.

    Depending on if you will use BUSY indicator or not, you will need 17 or 16 clock cycles; say 17 clock cycles need to occure within the aquisition phase, that means the period will be:

    700ns/ 17 = 41.17ns or 24.28 Mhz.

    Overall, to run the device at full sampling rate, the SCLK will need to be at ~25Mhz, which is the maximum clock frequency.

    Figures 47 and 49 of the datasheet will prove helpful

    Regards

    Cynthia