• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 46 subscribers
  • Views 968 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TFP401A Latency Question

TomC
Prodigy 30 points
Other Parts Discussed in Thread: TFP401A

Has the TFP401A been characterised sufficiently to know the delay between a complete pixel data packet on the RX line been received and the subsequent transition on the parralel data output? (ie propagation delay through the latch, data recovery/synchronization and TMDS decoder?)

Thanks

Tom

  • 0
    TI__Mastermind 43875 points

    No since this is not a useful parameter. Having said this it will most likely be completely deterministic in terms of clock cycles but there may be jitter introduced due to PLL tracking.

    The propagation delay is not usually useful in any way since the output data is synchronous to the output pixel clock and you should not/cannot actively monitor the received DVI clock due to impedance matching requirements.

    What is the actual issue you are trying to solve?

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 30 points

    We are using the receiver as part of an augmented reality display and need to know the latency of each part of the video path. I appreciate the contribution will be very small but I still require the information. 

  • 0 in reply to TomC
    TI__Mastermind 43875 points

    Unfortunately we don't have the information readily available.

    It will be in the 2 to 3 pixel clock cycle range and will be deterministic.

    BR,

    Steve