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CCS/AM5716: how to measure cpu cycles for Cortex-M4

Kzk
Genius 5785 points

Part Number: AM5716

Tool/software: Code Composer Studio

Hello,

I'd like to measure the number of CPU cycles of Cortex-M4 in AM5716. The menu Run->Clock in CCS is greyed out. Also, Count Event is not displayed in Breakpoints. Both functions are available for Cortex-A15. What can I do?

Regards,
Kazu

  • 0
    TI__Guru**** 171659 points

    Kazu,

    Please use the SCTM Function module. It allows you to count many internal details apart from clock cycles.

    One detail: it seems the auto-refresh for this counter is not working well, forcing you to refresh (Right-click → Refresh) to see the counter to update. 

    Hope this helps,
    Rafael

  • 0 in reply to desouza
    Genius 5785 points

    Rafael,

    Thank you for your answer. I create SCTM as below. I don't edit it and use as default. According to the GEL file, IPU1 is operating at 212 MHz. The one clock cycle of SCTM is 4.7 ns (1/212 MHz), isn't it?

    The program of Cortex-M4 is mapped to DDR3. When CM4 executes one nop, Count increases by several hundred cycles. And Count increases by 16 or 20 cycles in the case of Unicache and AMMU enabled. Do you think if these value are appropriate?

    Regards,

    Kazu

  • 0 in reply to Kzk
    Genius 5785 points

    Hello,

    Could you give me some advice about clock cycles?

    Regards,

    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 171659 points
    Kazu,

    Sorry about the delay.

    >>I create SCTM as below. I don't edit it and use as default. According to the GEL file, IPU1 is operating at 212 MHz. The one clock cycle of SCTM is 4.7 ns (1/212 MHz), isn't it?

    You are correct about the clock cycle time.

    >>The program of Cortex-M4 is mapped to DDR3. When CM4 executes one nop, Count increases by several hundred cycles. And Count increases by 16 or 20 cycles in the case of Unicache and AMMU enabled. Do you think if these value are appropriate?

    Despite I am not a device expert, I know for other architectures (AM335x, for example) the latency of accessing external memory can easily reach more than one hundred cycles - the cache has a lot less latency given it uses the internal bus.

    Reference: sections 6 and 7 of
    processors.wiki.ti.com/.../Profile_clock_in_CCS

    Hope this helps,
    Rafael