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CCS/EVMK2H: CCS 7.3.0.00019 Cache view displays incorrect information for a C66 core

Part Number: EVMK2H

Tool/software: Code Composer Studio

Using CCS 7.3.0.00019 was attempting to analyse the cache usage for a SYS/BIOS program running on a C66 core of a 66AK2H14. A custom SYS/BIOS platform is in use where the program runs in DDR3 address space from 0x80000000 to 0xffffffff and the L2 cache size is set to the maximum of 1024K.

The cache usage displayed in the Cache view appears incorrect, but the cache usage shown in the Memory Browser looks valid. Some specific examples are:

1) The Cache View only displays doesn't display some line addresses as in the L1D cache which the Memory Browser does:

The Cache View has been been ordered as increasing Line Start Address. The Cache view shows 0xFFE0EC00 - 0xFFE0EC3F in the L1D cache, and then the next line address in the L1D cache is 0xFFE0ED00 - 0xFFE0ED3F. Whereas the Memory Browser shows addresses 0xFFE0EC00 - 0xFFE0ED3F as in the L1D cache.

2) The Cache view can display invalid L1D entries:

The Cache view shows entries in the L1D cache around line address zero. Where address zero isn't used by the program, and the Memory Browser reports that address zero can't be accessed. The Cache view is also displaying invalid "Way" values, since for the L1D Way can only be zero or one.

3) The Cache view never shows any data in the L2 cache, but the Memory Browser view does:

I think the CCS 7.3 Cache view is incorrectly interpreting the contents of the Cache Tag RAM for a C66 core.

  • Chester Gillon said:
    I think the CCS 7.3 Cache view is incorrectly interpreting the contents of the Cache Tag RAM for a C66 core.

    CCS 7.4.0.00010 (beta) and CCS 6.2.0.00050 show the same problem as CCS 7.3, in that the Cache view displays incorrect information.

  • Hello Chester,

    Thank you for reporting this issue. We are currently investigating. Given that you see the issue as far back as 6.2.0, it appears it has existed for quite some time. I will keep you posted of our findings

    Thanks

    ki

  • Hello Chester,
    I have not be able to reproduce the issues described. I am also using CCSv7.3.0.00019 with a SYS/BIOS program running from DDR3 (0x80000000) on a C66x core. However, I am using a different target (C6657). Everything looks fine so far. Can you provide a small test case?

    Thanks
    ki

  • Ki-Soo Lee said:
    Can you provide a small test case?

    Attached is the test program which I used to capture the screen shots in the first post when stepping the taskFxn() function.

    66AK2H14_C66_max_sysbios_heap_size.zip is the SYS/BIOS program.

    5314.platforms.zip contains the custom platform used, to be placed in the same workspace as the SYS/BIOS program.

    The program was run in a 66AK2H14 C66 core of a EVMK2H using the on-board XDS200 debug probe.

    Ki-Soo Lee said:
    I am also using CCSv7.3.0.00019 with a SYS/BIOS program running from DDR3 (0x80000000) on a C66x core. However, I am using a different target (C6657). Everything looks fine so far.

    I have seen the problem on a number of programs running on a C66x core of a 66AK2H14. Could try and repeat the problem on some different targets, but won't have access to the hardware until the weekend.

  • Thank you Chester. I was able to gain access to a Keystone 2 target (K2G EVM) and was able to reproduce the first two issues at least. I filed a bug against the Cache view. Tracking ID: CCDSK-3007

    Thanks
    ki
  • I was able to reproduce the third issue on a K2HEVM here and appended the details to the bug report.

    Cheers,
    Rafael
  • Ki-Soo Lee said:
    I am also using CCSv7.3.0.00019 with a SYS/BIOS program running from DDR3 (0x80000000) on a C66x core. However, I am using a different target (C6657). Everything looks fine so far.

    Using CCS v7.3.0.00019 with a SYS/BIOS program running in a C66x core of an AM5728, the CCS Cache View displays correct information:

    This confirms the problem is sensitive to the target.