Part Number: EVMK2H
Tool/software: Code Composer Studio
Using CCS 7.3.0.00019 was attempting to analyse the cache usage for a SYS/BIOS program running on a C66 core of a 66AK2H14. A custom SYS/BIOS platform is in use where the program runs in DDR3 address space from 0x80000000 to 0xffffffff and the L2 cache size is set to the maximum of 1024K.
The cache usage displayed in the Cache view appears incorrect, but the cache usage shown in the Memory Browser looks valid. Some specific examples are:
1) The Cache View only displays doesn't display some line addresses as in the L1D cache which the Memory Browser does:
The Cache View has been been ordered as increasing Line Start Address. The Cache view shows 0xFFE0EC00 - 0xFFE0EC3F in the L1D cache, and then the next line address in the L1D cache is 0xFFE0ED00 - 0xFFE0ED3F. Whereas the Memory Browser shows addresses 0xFFE0EC00 - 0xFFE0ED3F as in the L1D cache.
2) The Cache view can display invalid L1D entries:
The Cache view shows entries in the L1D cache around line address zero. Where address zero isn't used by the program, and the Memory Browser reports that address zero can't be accessed. The Cache view is also displaying invalid "Way" values, since for the L1D Way can only be zero or one.
3) The Cache view never shows any data in the L2 cache, but the Memory Browser view does:
I think the CCS 7.3 Cache view is incorrectly interpreting the contents of the Cache Tag RAM for a C66 core.